Flash memory with millimeter wave host interface and method for use therewith

ABSTRACT

A host interface module includes a millimeter wave transceiver that is coupled to wirelessly communicate read commands, write commands, read data and write data between a flash memory device and a host device over a millimeter wave communication path in accordance with a host interface protocol. A protocol conversion module is coupled to convert the read commands, the write commands and the write data from the host interface protocol and to convert the read data to the host interface protocol. A host module is coupled to decode the read commands and the write commands from the host device, to process the read commands to retrieve the read data from the flash memory and to process the write commands to write the write data to the flash memory.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is related to the following patent applicationsthat commonly assigned and are concurrently filed herewith:

U.S. application Ser. No. 11/888,022, entitled, PROGRAMMABLE LOGICDEVICE WITH MILLIMETER WAVE INTERFACE AND METHOD FOR USE THEREWITH; nowpending

U.S. application Ser. No. 11/830,744, entitled, DISK CONTROLLER WITHMILLIMETER WAVE HOST INTERFACE AND METHOD FOR USE THEREWITH; nowabandoned the contents of which are expressly incorporated herein byreference thereto.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

This invention relates generally to flash memory devices and integratedcircuits used therein.

2. Description of Related Art

Communication systems are known to support wireless and wire linedcommunications between wireless and/or wire lined communication devices.Such communication systems range from national and/or internationalcellular telephone systems to the Internet to point-to-point in-homewireless networks to radio frequency identification (RFID) systems. Eachtype of communication system is constructed, and hence operates, inaccordance with one or more communication standards. For instance,wireless communication systems may operate in accordance with one ormore standards including, but not limited to, RFID, IEEE 802.11,Bluetooth™ Technology (henceforth referred to as “Bluetooth” in thedescription), advanced mobile phone services (AMPS), digital AMPS,global system for mobile communications (GSM), code division multipleaccess (CDMA), local multi-point distribution systems (LMDS),multi-channel-multi-point distribution systems (MMDS), and/or variationsthereof.

Depending on the type of wireless communication system, a wirelesscommunication device, such as a cellular telephone, two-way radio,personal digital assistant (PDA), personal computer (PC), laptopcomputer, home entertainment equipment, RFID reader, RFID tag, et ceteracommunicates directly or indirectly with other wireless communicationdevices. For direct communications (also known as point-to-pointcommunications), the participating wireless communication devices tunetheir receivers and transmitters to the same channel or channels (e.g.,one of the plurality of radio frequency (RF) carriers of the wirelesscommunication system) and communicate over that channel(s). For indirectwireless communications, each wireless communication device communicatesdirectly with an associated base station (e.g., for cellular services)and/or an associated access point (e.g., for an in-home or in-buildingwireless network) via an assigned channel. To complete a communicationconnection between the wireless communication devices, the associatedbase stations and/or associated access points communicate with eachother directly, via a system controller, via the public switch telephonenetwork, via the Internet, and/or via some other wide area network.

For each wireless communication device to participate in wirelesscommunications, it includes a built-in radio transceiver (i.e., receiverand transmitter) or is coupled to an associated radio transceiver (e.g.,a station for in-home and/or in-building wireless communicationnetworks, RF modem, etc.). As is known, the receiver is coupled to theantenna and includes a low noise amplifier, one or more intermediatefrequency stages, a filtering stage, and a data recovery stage. The lownoise amplifier receives inbound RF signals via the antenna andamplifies then. The one or more intermediate frequency stages mix theamplified RF signals with one or more local oscillations to convert theamplified RF signal into baseband signals or intermediate frequency (IF)signals. The filtering stage filters the baseband signals or the IFsignals to attenuate unwanted out of band signals to produce filteredsignals. The data recovery stage recovers raw data from the filteredsignals in accordance with the particular wireless communicationstandard.

As is also known, the transmitter includes a data modulation stage, oneor more intermediate frequency stages, and a power amplifier. The datamodulation stage converts raw data into baseband signals in accordancewith a particular wireless communication standard. The one or moreintermediate frequency stages mix the baseband signals with one or morelocal oscillations to produce RF signals. The power amplifier amplifiesthe RF signals prior to transmission via an antenna.

In most applications, radio transceivers are implemented in one or moreintegrated circuits (ICs), which are inter-coupled via traces on aprinted circuit board (PCB). The radio transceivers operate withinlicensed or unlicensed frequency spectrums. For example, wireless localarea network (WLAN) transceivers communicate data within the unlicensedIndustrial, Scientific, and Medical (ISM) frequency spectrum of 900 MHz,2.4 GHz, and 5 GHz. While the ISM frequency spectrum is unlicensed thereare restrictions on power, modulation techniques, and antenna gain.

As IC fabrication technology continues to advance, ICs will becomesmaller and smaller with more and more transistors. While thisadvancement allows for reduction in size of electronic devices, it doespresent a design challenge of providing and receiving signals, data,clock signals, operational instructions, etc., to and from a pluralityof ICs of the device. Currently, this is addressed by improvements in ICpackaging and multiple layer PCBs. For example, ICs may include aball-grid array of 100-200 pins in a small space (e.g., 2 to 20millimeters by 2 to 20 millimeters). A multiple layer PCB includestraces for each one of the pins of the IC to route to at least one othercomponent on the PCB. Clearly, advancements in communication between ICsare needed to adequately support the forth-coming improvements in ICfabrication.

As is known, many varieties of disk drives, such as magnetic disk drivesare used to provide data storage for a host device, either directly, orthrough a network such as a storage area network (SAN) or networkattached storage (NAS). Typical host devices include stand alonecomputer systems such as a desktop or laptop computer, enterprisestorage devices such as servers, storage arrays such as a redundantarray of independent disks (RAID) arrays, storage routers, storageswitches and storage directors, and other consumer devices such as videogame systems and digital video recorders. These devices provide highstorage capacity in a cost effective manner. The disk drive includes ahost interface module that provides control, status and data transferbetween the host device and the disk drive.

Field programmable gate arrays contain a plurality of logic blocks thatare configurable via programmable interconnects to implement one or morearbitrary logic functions. In this fashion, complex devices can beimplemented and programmed in the field.

Flash memory devices such as NOR flash and NAND flash devices canprovide non-volatile storage of digital data. These devices areimplemented in a wide variety of host devices, particularly in datastorage and firmware applications.

The limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of ordinary skill in the artthrough comparison of such systems with the present invention.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to apparatus and methods of operationthat are further described in the following Brief Description of theDrawings, the Detailed Description of the Invention, and the claims.Other features and advantages of the present invention will becomeapparent from the following detailed description of the invention madewith reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

FIG. 1 presents a pictorial representation of a handheld audio unit 51in accordance with an embodiment of the present invention;

FIG. 2 presents a pictorial representation of a computer 52 inaccordance with an embodiment of the present invention;

FIG. 3 presents a pictorial representation of a wireless communicationdevice 53 in accordance with an embodiment of the present invention;

FIG. 4 presents a pictorial representation of a personal digitalassistant 54 in accordance with an embodiment of the present invention;

FIG. 5 presents a pictorial representation of a laptop computer 55 inaccordance with an embodiment of the present invention;

FIG. 6 presents a pictorial representation of a disk drive unit 100 inaccordance with an embodiment of the present invention;

FIG. 7 presents a block diagram representation of a disk controller 130in accordance with an embodiment of the present invention;

FIG. 8 presents a block diagram representation of a host interfacemodule 150 in accordance with an embodiment of the present invention;

FIG. 9 presents a block diagram representation of a configuration module60 in accordance with an embodiment of the present invention;

FIG. 10 presents a flowchart representation of a method in accordancewith an embodiment of the present invention;

FIG. 11 presents a block diagram representation of a flash memory 1230in accordance with an embodiment of the present invention;

FIG. 12 presents a block diagram representation of a host interfacemodule 1250 in accordance with an embodiment of the present invention;

FIG. 13 presents a flowchart representation of a method in accordancewith an embodiment of the present invention;

FIG. 14 presents a block diagram representation of a programmable logicdevice 1325 in accordance with an embodiment of the present invention;

FIG. 15 presents a block diagram representation of a programmable logicdevice 1325′ in accordance with an embodiment of the present invention;

FIG. 16 is a schematic block diagram of an embodiment of RF transceiver135 in accordance with the present invention;

FIG. 17 presents a block diagram representation of a protocol 1490 inaccordance with an embodiment of the present invention;

FIG. 18 presents a block diagram representation of a protocol 1490 inaccordance with an embodiment of the present invention;

FIG. 19 is a schematic block diagram of an embodiment of a millimeterwave interface 1080 in accordance with the present invention;

FIGS. 20-22 are diagrams of embodiments of intra-device wirelesscommunications via a millimeter wave interface in accordance with thepresent invention;

FIGS. 23-26 are schematic block diagrams of other embodiments of adevice in accordance with the present invention;

FIG. 27 is a diagram of an embodiment of a frame of an intra-devicewireless communication in accordance with the present invention;

FIGS. 28-32 are schematic block diagrams of other embodiments of adevice in accordance with the present invention;

FIGS. 33-35 are schematic block diagrams of embodiments of an RFtransceiver device in accordance with the present invention;

FIG. 36 is a diagram of an example of a frame of an RF transceiverdevice wireless communication in accordance with the present invention;

FIG. 37 is a logic diagram of an embodiment of a method of resourceallocation for an intra-device wireless communication in accordance withthe present invention;

FIG. 38 is a diagram of another example of a frame of an RF transceiverdevice wireless communication in accordance with the present invention;

FIG. 39 is a diagram of an example of mapping data of an RF transceiverdevice wireless communication in accordance with the present invention;

FIGS. 40 and 41 are schematic block diagrams of other embodiments of anRF transceiver device in accordance with the present invention;

FIG. 42 is a schematic block diagram of another embodiment of a devicein accordance with the present invention;

FIG. 43 is a logic diagram of a method for switching within a deviceaccordance with the present invention;

FIGS. 44-46 are diagrams of embodiments of a device in accordance withthe present invention;

FIG. 47 is a diagram of an embodiment of an intra-device RF buscommunication accordance with the present invention;

FIG. 48 is a schematic block diagram of another embodiment of a devicein accordance with the present invention;

FIGS. 49 and 50 are diagrams of embodiments of a device in accordancewith the present invention;

FIG. 51 is a schematic block diagram of an embodiment of a portion of anRF bus transceiver module in accordance with the present invention;

FIG. 52 is a diagram of an embodiment of an inductor and/or transformeraccordance with the present invention;

FIG. 53 is a diagram of an embodiment of a capacitor accordance with thepresent invention;

FIGS. 54 and 55 are diagrams of embodiments of an IC in accordance withthe present invention;

FIG. 56 is a schematic block diagram of an embodiment of an RF buscontroller in accordance with the present invention;

FIG. 57 is a logic diagram of method for controlling access to an RF busin accordance with the present invention;

FIG. 58 is a diagram of another embodiment of a frame of an RF buscommunication in accordance with the present invention;

FIG. 59 is a logic diagram of method for determining RF bus resourceavailability in accordance with the present invention;

FIG. 60 is a logic diagram of another method for controlling access toan RF bus in accordance with the present invention;

FIG. 61 is a schematic block diagram of another embodiment of a devicein accordance with the present invention;

FIG. 62 is a logic diagram of another method for controlling access toan RF bus in accordance with the present invention;

FIG. 63 is a logic diagram of another method for controlling access toan RF bus in accordance with the present invention;

FIG. 64 is a schematic block diagram of an embodiment of an RF bustransceiver in accordance with the present invention;

FIG. 65 is a logic diagram of method for RF bus transmitting inaccordance with the present invention;

FIG. 66 is a logic diagram of method for RF bus receiving in accordancewith the present invention;

FIG. 67 is a logic diagram of method for determining whether informationis to be transmitted via an RF bus in accordance with the presentinvention;

FIG. 68 is a schematic block diagram of an embodiment of a transmittersection of an RF bus transceiver in accordance with the presentinvention;

FIGS. 69-71 are schematic block diagrams of embodiments of anup-conversion module of a transmitter section in accordance with thepresent invention; and

FIG. 72 is a schematic block diagram of an embodiment of a receiversection of an RF bus transceiver in accordance with the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 presents a pictorial representation of a handheld audio unit 51in accordance with an embodiment of the present invention. Inparticular, handheld audio unit 51 can include a magnetic hard disk asdescribed in conjunction with FIGS. 6-10 and/or a flash memory device asdescribed in conjunction with FIGS. 11-13 that provides general storageor storage of audio content such as motion picture expert group (MPEG)audio layer 3 (MP3) files or Windows Media Architecture (WMA) files,video content such as MPEG4 files for playback to a user, and/or anyother type of information that may be stored in a digital format. Inaddition or in the alternative, handheld audio unit 51 includes aprogrammable logic device as will be described in conjunction with FIG.14 or 15 that implements one or more functions of the device.

FIG. 2 presents a pictorial representation of a computer 52 inaccordance with an embodiment of the present invention. In particular,computer 52 can include a magnetic hard disk as described in conjunctionwith FIGS. 6-10 and/or a flash memory device as described in conjunctionwith FIGS. 11-13. In addition or in the alternative, computer 52includes a programmable logic device as will be described in conjunctionwith FIG. 14 or 15 that implements one or more functions of the device.Computer 52 can be a desktop computer, or an enterprise storage devicesuch as a server of a host computer that is attached to a storage arraysuch as a redundant array of independent disks (RAID) array, storagerouter, edge router, storage switch and/or storage director.

FIG. 3 presents a pictorial representation of a wireless communicationdevice 53 in accordance with an embodiment of the present invention. Inparticular, wireless communication device 53 can include a magnetic harddisk as described in conjunction with FIGS. 6-10 and/or a flash memorydevice as described in conjunction with FIGS. 11-13 that providesgeneral storage or storage of audio content such as motion pictureexpert group (MPEG) audio layer 3 (MP3) files or Windows MediaArchitecture (WMA) files, video content such as MPEG4 files, JPEG (jointphotographic expert group) files, bitmap files and files stored in othergraphics formats that may be captured by an integrated camera ordownloaded to the wireless communication device 53, emails, webpageinformation and other information downloaded from the Internet, addressbook information, and/or any other type of information that may bestored in a digital format. In addition or in the alternative, wirelesscommunication device 53 includes a programmable logic device as will bedescribed in conjunction with FIG. 14 or 15 that implements one or morefunctions of the device.

In an embodiment of the present invention, wireless communication device53 is capable of communicating via a wireless telephone network such asa cellular, personal communications service (PCS), general packet radioservice (GPRS), global system for mobile communications (GSM), andintegrated digital enhanced network (iDEN) or other wirelesscommunications network capable of sending and receiving telephone calls.Further, wireless communication device 53 is capable of communicatingvia the Internet to access email, download content, access websites, andprovide streaming audio and/or video programming. In this fashion,wireless communication device 53 can place and receive telephone calls,text messages such as emails, short message service (SMS) messages,pages and other data messages that can include attachments such asdocuments, audio files, video files, images and other graphics.

FIG. 4 presents a pictorial representation of a personal digitalassistant 54 in accordance with an embodiment of the present invention.In particular, personal digital assistant 54 can include a magnetic harddisk as described in conjunction with FIGS. 6-10 and/or a flash memorydevice as described in conjunction with FIGS. 11-13 that providesgeneral storage or storage of audio content such as motion pictureexpert group (MPEG) audio layer 3 (MP3) files or Windows MediaArchitecture (WMA) files, video content such as MPEG4 files, JPEG (jointphotographic expert group) files, bitmap files and files stored in othergraphics formats that may be captured by an integrated camera ordownloaded to the wireless communication device 53, emails, webpageinformation and other information downloaded from the Internet, addressbook information, and/or any other type of information that may bestored in a digital format. In addition or in the alternative, personaldigital assistant 54 includes a programmable logic device as will bedescribed in conjunction with FIG. 14 or 15 that implements one or morefunctions of the device.

FIG. 5 presents a pictorial representation of a laptop computer 55 inaccordance with an embodiment of the present invention. In particular,laptop computer 55 can include a magnetic hard disk as described inconjunction with FIGS. 6-10 and/or a flash memory device as described inconjunction with FIGS. 11-13 that provides general purpose storage forany type of information in digital format. In addition or in thealternative, laptop computer 55 includes a programmable logic device aswill be described in conjunction with FIG. 14 or 15 that implements oneor more functions of the device.

FIG. 6 presents a pictorial representation of a disk drive unit 100 inaccordance with an embodiment of the present invention. In particular,disk drive unit 100 includes a disk 102 that is rotated by a servo motor(not specifically shown) at a velocity such as 3600 revolutions perminute (RPM), 4200 RPM, 4800 RPM, 5400 RPM, 7200 RPM, 10,000 RPM, 15,000RPM, however, other velocities including greater or lesser velocitiesmay likewise be used, depending on the particular application andimplementation in a host device. In an embodiment of the presentinvention, disk 102 can be a magnetic disk that stores information asmagnetic field changes on some type of magnetic medium or an opticaldisk drive that stores and retrieves information optically. The mediumcan be a rigid or nonrigid, removable or nonremovable, that comprises oris coated with magnetic material or material that can be opticallywritten and read.

Disk drive unit 100 further includes one or more read/write heads 104that are coupled to arm 106 that is moved by actuator 108 over thesurface of the disk 102 either by translation, rotation or both. In anembodiment of the present invention, the read/write heads 104 include awrite element that writes data on the disk via longitudinal magneticrecording, perpendicular magnetic recording or other magneticorientation or by optical methods.

A disk controller 130 is included for controlling the read and writeoperations to and from the drive, for controlling the speed of the servomotor and the motion of actuator 108, and for providing an interface toand from the host device 50, such as handheld audio unit 51 computer 52,wireless communication device 53, personal digital assistant 54 laptopcomputer 55 or other host device, via a connector such as integratedconnector 96, cable connector 98 or via a wireless interface such as amillimeter wave interface.

Disk controller 130 includes one or more functions or features of thepresent invention, as described in further detail in conjunction withthe figures that follow.

FIG. 7 presents a block diagram representation of a disk controller 130in accordance with an embodiment of the present invention. Inparticular, disk controller 130 includes a read/write channel 140 forreading and writing data to and from disk 102 through read/write heads104. Disk formatter 125 is included for controlling the formatting ofdata and provides clock signals and other timing signals that controlthe flow of the data written to, and data read from disk 102, servoformatter 120 provides clock signals and other timing signals based onservo control data read from disk 102, device controllers 105 controlthe operation of drive devices 109 such as actuator 108 and the servomotor, etc. Host interface module 150 receives read and write commandsfrom host device 50, receives data to be written to the disk 102,transmits data read from disk 102 and provides status along with othercontrol information in accordance with a host interface protocol. In anembodiment of the present invention the host interface protocol caninclude, Advanced Technology Attachment (ATA)/Integrated DriveElectronics (IDE), Serial ATA (SATA), Fiber channel ATA (FATA), SmallComputer System Interface (SCSI), Enhanced IDE (EIDE), MultiMedia Card(MMC), Universal Serial Bus (USB), Serial Attached SCSI (SAS) andCompact Flash (CF) or any number of other host interface protocols,either open or proprietary that can be used for this purpose.

Disk controller 130 further includes a processing module 132 and memorymodule 134. Processing module 132 can be implemented using one or moremicroprocessors, micro-controllers, digital signal processors,microcomputers, central processing units, field programmable gatearrays, programmable logic devices, state machines, logic circuits,analog circuits, digital circuits, and/or any devices that manipulatessignals (analog and/or digital) based on operational instructions thatare stored in memory module 134. When processing module 132 isimplemented with two or more devices, each device can perform the samesteps, processes or functions in order to provide fault tolerance orredundancy. Alternatively, the function, steps and processes performedby processing module 132 can be split between different devices toprovide greater computational speed and/or efficiency.

Memory module 134 may be a single memory device or a plurality of memorydevices. Such a memory device may be a read-only memory, random accessmemory, volatile memory, non-volatile memory, static random accessmemory (SRAM), dynamic random access memory (DRAM), flash memory, cachememory, and/or any device that stores digital information. Note thatwhen the processing module 132 implements one or more of its functionsvia a state machine, analog circuitry, digital circuitry, and/or logiccircuitry, the memory module 134 storing the corresponding operationalinstructions may be embedded within, or external to, the circuitrycomprising the state machine, analog circuitry, digital circuitry,and/or logic circuitry. Further note that, the memory module 134 stores,and the processing module 132 executes operational instructions tocontrol the operation of drive devices 109, to arbitrate the executionof read and write commands, the flow of data between the host interfacemodule 150 and the read/write channel 140 and to perform other functionsof the drive.

Disk controller 130 includes a plurality of modules, in particular,device controllers 105, processing module 132, memory module 134,read/write channel 140, disk formatter 125, servo formatter 120 and hostinterface module 150 that are interconnected via buses 136 and 137. Eachof these modules can be implemented in hardware, firmware, software or acombination thereof, in accordance with the broad scope of the presentinvention. While a particular bus architecture is shown in FIG. 2 withbuses 136 and 137, alternative bus architectures that include either asingle bus configuration or additional data buses, further connectivity,such as direct connectivity between the various modules, are likewisepossible to implement the features and functions included in the variousembodiments of the present invention.

In an embodiment of the present invention, one or more modules of diskcontroller 130 are implemented as part of a system on a chip integratedcircuit. In an embodiment of the present invention, this system on achip integrated circuit includes a digital portion that can includeadditional modules such as protocol converters, linear block codeencoding and decoding modules, etc., and an analog portion that includesadditional modules, such as a power supply, disk drive motor amplifier,disk speed monitor, read amplifiers, etc. In a further embodiment of thepresent invention, the various functions and features of disk controller130 are implemented in a plurality of integrated circuit devices thatcommunicate and combine to perform the functionality of disk controller130.

In an embodiment of the present invention, the host interface moduleincludes a millimeter wave transceiver that is coupled to wirelesslycommunicate read commands, write commands, the read data and the writedata between the disk controller and the host device over a millimeterwave communication path. The host interface module can further includehardware, software or firmware that implements a plurality of differenthost interface protocols. This allows disk controller 130 to be designedas a generic device for multiple possible applications with differentstandard host devices. In this fashion, the host interface module can beconfigured for a particular application by selecting the particular hostinterface to be used or by detecting the particular host deviceconnected thereto. Further details regarding host interface module 150including additional novel features and functions will be described inconjunction with FIG. 8.

In addition, one or both of the buses 136 and 137 can be implementedwith a millimeter wave RF bus to allow wireless, rather that wiredconnectivity between various circuits of the disk controller 130. Forinstance, memory module 134, processing module 132 and host interfacemodule 150 can each include millimeter wave transceivers forcommunicating wirelessly between these modules. In addition, an RF buscontroller can be included to control and/or arbitrate the transfer ofdata between each of these circuits and/or the other components of diskcontroller 130. Further details regarding the operation of suchmillimeter wave RF buses, including several optional implementations andfeatures are described in conjunction with the millimeter wareinterfaces/RF buses presented in FIG. 19 and the figures that follow.

FIG. 8 presents a block diagram representation of a host interfacemodule 150 in accordance with an embodiment of the present invention. Inparticular, host interface module 150 includes a millimeter wavetransceiver 18 that is coupled to wirelessly communicate read commands,write commands, the read data and the write data between the diskcontroller 130 and the host device 150 over a millimeter wavecommunication path in accordance with a host interface protocol. Thehost interface protocol can include includes one or more of thefollowing protocols: AT Attachment (ATA), Serial ATA (SATA), Fiberchannel ATA (FATA), Small Computer System Interface (SCSI), IntegratedDrive Electronics (IDE), Enhanced IDE (EIDE), MultiMedia Card (MMC),Universal Serial Bus (USB), Serial Attached SCSI (SAS) and Compact Flash(CF), or other data protocols, either standard or proprietary forcommunication between a memory device and a host device.

Protocol conversion module 11 is coupled to convert the read commands,the write commands and the write data from the host interface protocoland to convert the read data to the host interface protocol. A hostmodule 20 is coupled to decode the read commands and the write commandsfrom the host device 50, to process the read commands to retrieve theread data from the disk drive via the read/write channel 140 and toprocess the write commands to write the write data to the disk drive 100via the read/write channel 140.

As discussed in conjunction with FIG. 7, the host interface module 150can further implement a plurality of host interface protocols. Thisallows disk controller 130 to be designed as a generic device formultiple possible applications with different standard host devices. Inparticular, host interface module 150 includes a plurality of protocolconversion modules 11, 13, 15. Each of the plurality of protocolconversion modules, when coupled to a corresponding host device 50, 50′or 50″, is operable to accept read and write commands and transfer datato and from the corresponding host device in a corresponding one of aplurality of host interface protocols. Multiplexer 6 selectively couplesa particular protocol conversion module 11, 13 or 15 to the host module20 in response to a selection signal 40. A system interface 30 isoptionally included to couple the host module 20 to processing module132 and memory 134 of the disk controller 130, such as via 136 or bus137. Host module 20 decodes read and write commands from a particularhost device 50, 50′ and/or 50″ and transports data written to and readfrom the disk drive unit 100 via the protocol conversion module that iscoupled to that host device and, in the case of host device 50, viamillimeter wave transceiver 18.

In an embodiment of the present invention, each of the plurality ofprotocol conversion modules 11, 13, 15 implements a different hostinterface protocol such ATA, SATA, FATA, SCSI. IDE, EIDE, MMC, FC, etc.In addition, the plurality of protocol conversion modules 13 and 15 caninclude a wired coupling, such as connector 96, cable connector 98, orother connection or coupling, with physical attributes and/or pinconfiguration selected in accordance with the particular host interfaceprotocol. In this fashion, a host device 50′ may communicate with diskdrive unit 100 via a protocol conversion module 11 that implements aSATA interface that is carried via a millimeter wave protocol betweenmillimeter wave transceiver 18 and a similar millimeter wave transceiverof the host device 50. In another implementation, a host device 50′ maycommunicate with disk drive unit 100 via a protocol conversion module 13that implements an ATA/IDE interface with a 40-pin connector. Further, ahost device 50″ may communicate with disk drive unit 100 via a protocolconversion module 15 that implements an SCSI interface with a 25-pinconnector. Selection signal 40 can be set in the factory or by the userto configure the host interface module 130 to operate with a particularhost device 50, 50′ or 50″ through the corresponding protocol conversionmodule 11, 13 or 15.

Host interface module 150, as a whole, converts incoming data andcommands from the host device 50, 50′ or 50″ in its corresponding hostinterface protocol, into data and commands in a format used by diskcontroller 130. Conversely, data from read from disk drive unit 100 isconverted by host interface module 150 from the format used by diskdrive unit 100 into the particular host interface protocol used by thehost device 50, 50′ or 50″. The format used by the disk controller canbe a standard format such as Direct Memory Access or any of a variety ofother formats that are used for this purpose.

The operation of host interface module 150 can be viewed in terms offour fundamental operations with the host device 50, 50′ and/or 50″:providing a physical layer interface to the host device, providing alink layer interface to the host device, providing a transport layerinterface to the host device, and provide command decoding of commandsfrom the host device. As opposed to replicating each of these fourfunctions in separate modules, the protocol conversion module 11, 13 and15 each provide provides physical layer and link layer interface, andthe host module 20 provides command decoding and transport layerinterface between the disk drive 100 and the host device that isattached thereto. In this fashion, the functionality of host module 20need not be replicated, saving potential circuitry, while providing fullfunctionality for each of the corresponding host interface protocols.

In this embodiment of the present invention, multiplexer 6 selectivelycouples one of the plurality of protocol conversion modules to theuniversal host module via a common parallel interface 8. This commonparallel interface 8 can conforms to the physical and link layerinterface of each of the protocol conversion modules 11, 13, and 15. Forinstance, common parallel interface 8 can include a separate line foreach unique signal line of the physical interfaces of each of theprotocol conversion modules 11, 13 and 15. In this fashion, the commonparallel interface includes the union of each of the signal linespresent on each of the plurality of protocol conversion modules 11, 13and 15.

In an embodiment, each of the plurality of protocol conversion modules11, 13 and 15 includes a corresponding task file register 10, 12 or 14that, when coupled to the host device 50, 50′ or 50″, can be written bythe host device. The host module 20 also includes a task file register24 that is copied from the task file register 10, 12 or 14, of theselected protocol conversion module 11, 13 and 15. This synchronizationof task file registers between the protocol conversion module(s) and thehost module 20 allows commands to be passed from the host device. Taskfile registers 10, 12, and 14 are implemented as specific locations in amemory of host interface module 150 that store commands, such as for DMAtransfers of a block of memory. In this implementation, the task fileregisters 10, 12, and 14 each contain an address field, such as a 16-bitaddress field and a count field, such as a 16-bit count field, and adata direction, that define the block of data to be transferred andwhether the operation is for a read or write. Task file register 24 ofhost module 20 is similarly implemented. Host module 20 further includesa buffer/FIFO 22 that buffers the read and write commands from the hostdevice in a buffer order, such as a first-in-first-out order.

In an embodiment of the present invention, host module 20 is implementedwith its own host processing engine, implemented using one or moremicroprocessors, micro-controllers, digital signal processors,microcomputers, central processing units, field programmable gatearrays, programmable logic devices, state machines, logic circuits,analog circuits, digital circuits, and/or any devices that manipulatessignal (analog and/or digital) based on operational instructions thatare stored in either memory module 134 or its own dedicated memory.

While one particular configuration for implementing multiple hostinterface protocols is shown, other implementations including theimplementation of a single host interface protocol or multiple hostinterface protocols through a single millimeter wave transceiver 18, canbe implemented within the broader scope of the present invention. Inaddition, while a single host module 20 operates universally to supportmultiple protocol conversion modules, similarly, multiple dedicated hostmodules can likewise be implemented.

FIG. 9 presents a block diagram representation of a configuration module60 in accordance with an embodiment of the present invention. In thisembodiment, selection signal 20 is automatically generated byconfiguration module 60 based on the particular host device that isconnected to host interface module 150. In particular, each protocolconversion module 11, 13 and 15 includes detection circuitry that, basedon the presence of supply voltages or signaling generated by the hostdevice, detects that a host device, such as either host device 50, hostdevice 50′ or host device 50″ is coupled thereto. In response, acorresponding one of the plurality of host detection signals 58 isasserted, and selection signal 40 is generated that causes multiplexer 6to couple the protocol conversion module that detected the presence of ahost device, to the universal host module 20. In the case of protocolconversion module 11, RF signals received by the millimeter wavetransceiver 18 via the millimeter wave communication path from hostdevice 50 can be trigger this selection. In an embodiment of the presentinvention, either millimeter wave transceiver 18 or the millimeter wavetransceiver of the host device 50 can initiate communications via abeacon signal or other signaling.

FIG. 10 presents a flowchart representation of a method in accordancewith an embodiment of the present invention. In particular, a method ispresented that can be used in conjunction with one or more of thefeatures or functions described in association with FIGS. 1-9. In step1200, read commands, write commands, read data and write data arewirelessly communicated between the disk drive and a host device over amillimeter wave communication path in accordance with a host interfaceprotocol. In step 1202, the read commands, the write commands and thewrite data are converted from the host interface protocol. In step 1204,the read data is converted to the host interface protocol.

In an embodiment of the present invention, the host interface protocolincludes at least one of: AT Attachment (ATA), Serial ATA (SATA), Fiberchannel ATA (FATA), Small Computer System Interface (SCSI), IntegratedDrive Electronics (IDE), Enhanced IDE (EIDE), MultiMedia Card (MMC),Universal Serial Bus (USB), Serial Attached SCSI (SAS) and Compact Flash(CF). The host interface protocol can operate in accordance with aprotocol stack having a physical layer, a link layer, a command layerand a transport layer interface between the disk controller and the hostdevice. Further, the physical layer and the link layer can operate inaccordance with a millimeter wave protocol.

FIG. 11 presents a block diagram representation of a flash memory device1230 in accordance with an embodiment of the present invention. Inparticular, flash memory device 1230 includes a memory module 1234, suchas NOR, NAND or other flash memory. A host interface module 1250 couplesthe memory module to a host device 50, such as handheld audio unit 51computer 52, wireless communication device 53, personal digitalassistant 54 laptop computer 55 or other host device. In particular,host interface module 1250 includes a millimeter wave transceiver forwirelessly communicating with the host device 50. Host module interfacemodule 1250 can includes a processing device 1232 to arbitrate theexecution of read and write commands and the flow of data between thehost interface module 1250 and the memory module 1234. In otherembodiments, a separate processing device, coupled to bus 1237, or in analternative configuration with or without bus coupling can be used forthis purpose.

Host interface module 1250, as a whole, converts incoming data andcommands from the host device 50 in the host interface protocol such asAT Attachment (ATA), Serial ATA (SATA), Fiber channel ATA (FATA), SmallComputer System Interface (SCSI), Integrated Drive Electronics (IDE),Enhanced IDE (EIDE), MultiMedia Card (MMC), Universal Serial Bus (USB),Serial Attached SCSI (SAS) and Compact Flash (CF), into data andcommands, such as DMA or any of a variety of other formats that are usedby flash memory device 1230 for this purpose. Conversely, data from readfrom memory module 1234 is converted by host interface module 150 fromthe format used by memory module 1234 into the particular host interfaceprotocol used by the host device 50.

In addition, bus 1237 can be implemented with a millimeter wave RF busto allow wireless, rather that wired connectivity between variouscircuits of the flash memory device 1230. For instance, memory module1234, and host interface module 1250 can each include millimeter wavetransceivers for communicating wirelessly between these modules. Inaddition, an RF bus controller can be included to control and/orarbitrate the transfer of data between each of these circuits and/or theother components of flash memory device 1230. Further details regardingthe operation of such millimeter wave RF buses, including severaloptional implementations and features are described in conjunction withthe millimeter ware interfaces/RF buses presented in FIG. 19 and thefigures that follow.

FIG. 12 presents a block diagram representation of a host interfacemodule 1250 in accordance with an embodiment of the present invention.In particular, host interface module 1250 operates in a similar fashionto host interface module 150 when implemented with a single protocolconversion module. Host interface module 1250 includes a millimeter wavetransceiver 1218 coupled to wirelessly communicate read commands, writecommands, read data and write data between the flash memory device 1230and the host device 50 over a millimeter wave communication path inaccordance with a host interface protocol. Protocol conversion module1211 is coupled to convert the read commands, the write commands and thewrite data from the host interface protocol and to convert the read datato the host interface protocol. Host module is coupled to decode theread commands and the write commands from the host device 50, to processthe read commands to retrieve the read data from the memory module 1234and to process the write commands to write the write data to the memorymodule 1234.

Host module 1220, like host module 20, can include a processing deviceto arbitrate the execution of read and write commands and the flow ofdata between the host interface module 1250 and the memory module 1234.Protocol conversion module 1211 with task file register 1210, hostmodule 1220 with buffer/FIFO 1222 and task file register 1224, andsystem interface 1225 can operate in a similar fashion to protocolconversion module 11 with task file register 10, host module 20 withbuffer/FIFO 22 and task file register 24, and optional system interface30 to read data from and write data to memory module 1234 based oncommands from host module 50.

The operation of host interface module 1250 can be viewed in terms offour fundamental operations with the host device 50: providing aphysical layer interface to the host device, providing a link layerinterface to the host device, providing a transport layer interface tothe host device, and provide command decoding of commands from the hostdevice. Protocol conversion module 1211 provides physical layer and linklayer interface, and the host module 1220 provides command decoding andtransport layer interface between the memory module 1234 and the hostdevice 50 that is attached thereto. In an embodiment of the presentinvention, the host interface protocol operates in accordance with aprotocol stack having a physical layer, a link layer, a command layerand a transport layer interface between the flash memory device 1230 andthe host device 50. In particular, the physical layer and the link layercan operate in accordance with a millimeter wave protocol of millimeterwave transceiver 1218

In an embodiment, protocol conversion module 1211 includes a task fileregister 1210, that can be written by the host device 50. The hostmodule 1220 also includes a task file register 1224 that is copied fromthe task file register 1210. This synchronization of task file registersbetween the protocol conversion module 1211 and the host module 1220allows commands to be passed from the host device 50. Task file register1210 is implemented as specific locations in a memory of host interfacemodule 1250 that store commands, such as for DMA transfers of a block ofmemory. In this implementation, the task file register 1210 contains anaddress field, such as a 16-bit address field and a count field, such asa 16-bit count field, and a data direction, that define the block ofdata to be transferred and whether the operation is for a read or write.Task file register 1224 of host module 1220 is similarly implemented.Host module 1220 further includes a buffer/FIFO 1222 that buffers theread and write commands from the host device 50 in a buffer order, suchas a first-in-first-out order.

FIG. 13 presents a flowchart representation of a method in accordancewith an embodiment of the present invention. In particular, a method ispresented that can be used in conjunction with one or more of thefeatures or functions described in association with FIGS. 11-12. In step1300, read commands, write commands, read data and write data arewirelessly communicated between a flash memory and a host device over amillimeter wave communication path in accordance with a host interfaceprotocol. In step 1302, the read commands, the write commands and thewrite data are converted from the host interface protocol. In step 1304,the read data are converted to the host interface protocol.

In an embodiment of the present invention, the host interface protocolincludes at least one of: AT Attachment (ATA), Serial ATA (SATA), Fiberchannel ATA (FATA), Small Computer System Interface (SCSI), IntegratedDrive Electronics (IDE), Enhanced IDE (EIDE), MultiMedia Card (MMC),Universal Serial Bus (USB), Serial Attached SCSI (SAS) and Compact Flash(CF), and operates in accordance with a protocol stack having a physicallayer, a link layer, a command layer and a transport layer interfacebetween the flash memory and the host device. The physical layer and thelink layer can operate in accordance with a millimeter wave protocol.

FIG. 14 presents a block diagram representation of a programmable logicdevice 1325 in accordance with an embodiment of the present invention.In particular, programmable logic device (PLD) 1325 is a fieldprogrammable gate array, programmable logic array, complex programmablelogic device or other programmable circuit that includes at least oneinput port and at least one output port, such as I/O ports 1340 and1342. The functionality of PLD 1325 is performed by a plurality ofconfigurable blocks 1330, 1331, such as logic blocks, memory elements,more complex functional blocks such as multipliers, dividers, filters,etc. that can be configured, via connection matrix 1322 to performcomplex logic functions on input data 1344 to produce output data 1346.A program interface module 1320 is coupled to configure the plurality ofconfigurable blocks 1330, 1331, and the I/O ports 1340, 1342 inaccordance with a configuration file 1315.

In an embodiment of the present invention, a millimeter wave transceiver1338 is coupled to wirelessly receive input data at the at least oneinput port and to wirelessly send output data 1346 from the at least oneoutput port over a millimeter wave communication path in accordance witha millimeter wave protocol in conjunction with a millimeter wavetransceiver of a host device, such as handheld audio unit 51, computer52, wireless communication device 53, personal digital assistant 54,laptop computer 55 or other host device. The millimeter wave transceiver1338 can include a protocol conversion module coupled to convert theinput data 1344 from a millimeter wave protocol and to convert theoutput data 1346 to the millimeter wave protocol for communication overthe millimeter wave communication path.

The PLD 1325 can include a memory 1332 and a processor 1334, operablycoupled to the memory and the program interface module, and configurablycoupled in accordance with the configuration file to at least one of theplurality of configurable blocks 1330, 1331. In this fashion, PLD 1325can be configured to perform more complicated software/firmwareoperations in conjunction with the configurable blocks 1330, 1331.

The program interface module 1320 can include a millimeter wavetransceiver 1318 that is coupled to wirelessly receive the configurationfile 1315 in accordance with the millimeter wave protocol, from anexternal device that is coupled to program the PLD 1325.

FIG. 15 presents a block diagram representation of a programmable logicdevice 1325′ in accordance with an embodiment of the present invention.In particular, a PLD 1325 is shown that includes many similar elementsto PLS 1325 that are referred to by common reference numerals. Inaddition, connection matrix 1322 is implemented via an millimeter waveRF bus 1348 to couple one or more of the plurality of configurableblocks 1330, 1331, the processor 1334, the memory 1332 and the I/O ports1340, 1342. The millimeter wave RF bus 1348 allows wireless, rather thatwired connectivity to configure the various circuits of PLS 1325′. Forinstance, circuits such as configurable blocks 1330, 1331, memory 1332,processor 1334, and I/O ports 1340, 1342 can each include millimeterwave transceivers for communicating wirelessly between these circuits.In addition, an RF bus controller can be included to control and/orarbitrate the transfer of data between each of these circuits. Furtherdetails regarding the operation of such millimeter wave RF buses,including several optional implementations and features are described inconjunction with the millimeter ware interfaces/RF buses presented inFIG. 19 and the figures that follow.

FIG. 16 is a schematic block diagram of an embodiment of RF transceiver135 in accordance with the present invention. The RF transceiver 135,such as millimeter wave transceivers 18, 1218, 1318, 1338, etc. includesan RF transmitter 139, and an RF receiver 137. The RF receiver 137includes a RF front end 140, a down conversion module 142 and a receiverprocessing module 144. The RF transmitter 139 includes a transmitterprocessing module 146, an up conversion module 148, and a radiotransmitter front-end 150.

As shown, the receiver and transmitter are each coupled to an antennathrough an off-chip antenna interface 171 and a diplexer (duplexer) 177,that couples the transmit signal 155 to the antenna to produce outboundRF signal 170 and couples inbound signal 152 to produce received signal153. Alternatively, a transmit/receive switch can be used in place ofdiplexer 177. While a single antenna is represented, the receiver andtransmitter may share a multiple antenna structure that includes two ormore antennas. In another embodiment, the receiver and transmitter mayshare a multiple input multiple output (MIMO) antenna structure,diversity antenna structure, phased array or other controllable antennastructure that includes a plurality of antennas. Each of these antennasmay be fixed, programmable, and antenna array or other antennaconfiguration. Also, the antenna structure of the wireless transceivermay depend on the particular standard(s) to which the wirelesstransceiver is compliant and the applications thereof.

In operation, the transmitter receives outbound data 162 that includesnon-realtime data or real-time data from a host device, such ascommunication device 10 or other source via the transmitter processingmodule 146. The transmitter processing module 146 packetizes outbounddata 162 in accordance with a millimeter wave protocol, either standardor proprietary, to produce baseband or low intermediate frequency (IF)transmit (TX) signals 164 that includes an outbound symbol stream thatcontains outbound data 162. The baseband or low IF TX signals 164 may bedigital baseband signals (e.g., have a zero IF) or digital low IFsignals, where the low IF typically will be in a frequency range of onehundred kilohertz to a few megahertz. Note that the processing performedby the transmitter processing module 146 can include, but is not limitedto, scrambling, encoding, puncturing, mapping, modulation, and/ordigital baseband to IF conversion.

The up conversion module 148 includes a digital-to-analog conversion(DAC) module, a filtering and/or gain module, and a mixing section. TheDAC module converts the baseband or low IF TX signals 164 from thedigital domain to the analog domain. The filtering and/or gain modulefilters and/or adjusts the gain of the analog signals prior to providingit to the mixing section. The mixing section converts the analogbaseband or low IF signals into up-converted signals 166 based on atransmitter local oscillation 168.

The radio transmitter front end 150 includes a power amplifier and mayalso include a transmit filter module. The power amplifier amplifies theup-converted signals 166 to produce outbound RF signals 170, which maybe filtered by the transmitter filter module, if included. The antennastructure transmits the outbound RF signals 170 to a targeted devicesuch as a RF tag, base station, an access point and/or another wirelesscommunication device via an antenna interface 171 coupled to an antennathat provides impedance matching and optional bandpass filtration.

The receiver receives inbound RF signals 152 via the antenna andoff-chip antenna interface 171 that operates to process the inbound RFsignal 152 into received signal 153 for the receiver front-end 140. Ingeneral, antenna interface 171 provides impedance matching of antenna tothe RF front-end 140, optional bandpass filtration of the inbound RFsignal 152.

The down conversion module 142 includes a mixing section, an analog todigital conversion (ADC) module, and may also include a filtering and/orgain module. The mixing section converts the desired RF signal 154 intoa down converted signal 156 that is based on a receiver localoscillation 158, such as an analog baseband or low IF signal. The ADCmodule converts the analog baseband or low IF signal into a digitalbaseband or low IF signal. The filtering and/or gain module high passand/or low pass filters the digital baseband or low IF signal to producea baseband or low IF signal 156 that includes a inbound symbol stream.Note that the ordering of the ADC module and filtering and/or gainmodule may be switched, such that the filtering and/or gain module is ananalog module.

The receiver processing module 144 processes the baseband or low IFsignal 156 in accordance with a millimeter wave protocol, eitherstandard or proprietary to produce inbound data 160. The processingperformed by the receiver processing module 144 can include, but is notlimited to, digital intermediate frequency to baseband conversion,demodulation, demapping, depuncturing, decoding, and/or descrambling.

In an embodiment of the present invention, receiver processing module144 and transmitter processing module 146 can be implemented via use ofa microprocessor, micro-controller, digital signal processor,microcomputer, central processing unit, field programmable gate array,programmable logic device, state machine, logic circuitry, analogcircuitry, digital circuitry, and/or any device that manipulates signals(analog and/or digital) based on operational instructions. Theassociated memory may be a single memory device or a plurality of memorydevices that are either on-chip or off-chip. Such a memory device may bea read-only memory, random access memory, volatile memory, non-volatilememory, static memory, dynamic memory, flash memory, and/or any devicethat stores digital information. Note that when the these processingdevices implement one or more of their functions via a state machine,analog circuitry, digital circuitry, and/or logic circuitry, theassociated memory storing the corresponding operational instructions forthis circuitry is embedded with the circuitry comprising the statemachine, analog circuitry, digital circuitry, and/or logic circuitry.

While the processing module 144 and transmitter processing module 146are shown separately, it should be understood that these elements couldbe implemented separately, together through the operation of one or moreshared processing devices or in combination of separate and sharedprocessing.

FIG. 17 presents a block diagram representation of a protocol 1490 inaccordance with an embodiment of the present invention. In particular, aprotocol 1490 is illustrated that can be used in conjunction withmillimeter wave transceivers 18 and 1218, etc. This protocol 1490contemporaneously operates in accordance with a plurality of differentprotocols, such as in a protocol stack or other multiple protocolarrangement that includes a physical layer, a link layer, a commandlayer and a transport layer. For instance, physical and link layer 1492can operate over the millimeter wave communication path in accordancewith a millimeter wave protocol. This millimeter wave protocol can carrya data payload via frames and/or packets with a header that includescontrol information. The data payload of the millimeter wave protocolcan include data formatted in accordance with host interface protocol1496 and memory protocol 1498 that cooperate to interface with a hostdevice such as host device 50 in a format that is recognized by the hostdevice and to transport data in accordance with read and write commands.It should be noted that a variety of different protocol structures canlikewise be used to transfer data between host device 50 and either diskdrive 100 or flash memory device 1230.

FIG. 18 presents a block diagram representation of a protocol 1490′ inaccordance with an embodiment of the present invention. In particular, aprotocol 1490′ is illustrated that can be used in conjunction withmillimeter wave transceivers 1318 and 1338, etc. This protocol 1490contemporaneously operates in accordance with a plurality of differentprotocols, such as in a protocol stack or other multiple protocolarrangement that includes a physical layer, a link layer, a commandlayer and a transport layer. As discussed in conjunction with FIG. 17,physical and link layer 1492 can operate over the millimeter wavecommunication path in accordance with a millimeter wave protocol. Thismillimeter wave protocol can carry a data payload via frames and/orpackets with a header that includes input data 1344, output data 1346,configuration file 1315 etc. The data payload of the millimeter waveprotocol can include data formatted in accordance with one or moreadditional protocols 1499 as is desirable for the transfer ofconfiguration file 1315, input data 1344 and output data 1346.

FIGS. 19-72 generally pertain to a millimeter wave interface 1080, suchas a millimeter wave RF bus, that may be used to interface circuitmodules of disk controller 130, flash memory device 1230 and PLD 1325′,regardless of whether these devices are implemented using separate ICsor circuit modules of a common IC. While generally described in terms ofthe interconnection of a processor, memory and peripheral devices, thisRF bus structure can likewise be applied to configurable blocks 1330,1331, I/O ports 1340, 1342, host interface module 1250 or any submodulesthereof, host interface module 150 or any submodules thereof,application specific integrated circuit (ASIC), analog to digitalconverter (ADC), digital to analog converter (DAC), digital logiccircuitry, analog circuitry, graphics processor or any other circuitmodules of disk controller 130, programmable logic device 1325′ and/orflash memory device 1230.

FIG. 19 is a schematic block diagram of an embodiment of a millimeterwave interface 1080 that interfaces a plurality of integrated circuits(ICs) 1084, 1086, and includes an RF bus controller 1088. In thisembodiment, IC 1084 includes a first radio frequency (RF) bustransceiver 1108 and IC 1086 includes a second RF bus transceiver 1110to support intra-device RF communications 1090 therebetween. Theintra-device RF communications 1090 may be RF data communications, RFinstruction communications, RF control signal communications, and/or RFinput/output communications. For example, data, control, operationalinstructions, and/or input/output signals (e.g., analog input signals,analog output signals, digital input signals, digital output signals)that are traditionally conveyed between ICs via traces on a printedcircuit board are, in millimeter wave interface 1080 transmitted via theintra-device RF communications 1090.

The intra-device RF communications 1090 may also include operatingsystem level communications and application level communications. Theoperating system level communications are communications that correspondto resource management of the millimeter wave interface 1080 loading andexecuting applications (e.g., a program or algorithm), multitasking ofapplications, protection between applications, device start-up,interfacing with a user of the millimeter wave interface 1080 etc. Theapplication level communications are communications that correspond tothe data conveyed, operational instructions conveyed, and/or controlsignals conveyed during execution of an application.

The RF bus controller 1088 is coupled to control the intra-device RFcommunications 1090 between the first and second RF bus transceivers1108, 1110. The RF bus controller 1088 may be a separate IC or it may beincluded in one of the ICs 1084, 1086. The functionality of the RF buscontroller 1088 will be described in greater detail with reference tothe figures that follow.

FIGS. 20-22 are diagrams of embodiments of intra-device wirelesscommunications 1090 being conveyed over different types of RFcommunication paths. In these embodiments, the antenna of each IC 1084,1086 is shown external to the IC for ease of illustration, but, in mostICs embodiments, the antenna will be in the IC.

FIG. 20 illustrates the millimeter wave interface 1080 further includinga supporting substrate 1094 that supports the ICs 1084, 1086. In thisembodiment, the intra-device RF communications 1090 occur over afree-space RF communication path 1096. In other words, the intra-deviceRF communications 1090 are conveyed via the air.

FIG. 21 illustrates the millimeter wave interface 1080 having thesupporting substrate 1094 including a waveguide RF communication path1098. In this embodiment, the intra-device RF communications 1090 occurvia the waveguide RF communication path 1098. The waveguide RFcommunication path 1098 may be formed in a micro-electromechanical (MEM)area of the supporting substrate 1094.

FIG. 22 illustrates the millimeter wave interface 1080 having thesupporting substrate 1094 including a plurality of dielectric layers1101, 1102. In this embodiment, the dielectric layers 1101 and 1102 havedifferent dielectric properties such that the border between dielectriclayer 1101 and dielectric layer 1102 reflect the RF signals transceivedby the ICs 1084, 1086. In this manner, dielectric layer 101 provides adielectric RF communication path 1100 for the intra-device RFcommunications 1090.

In an embodiment of millimeter wave interface 1080 the intra-device RFcommunications 1090 may occur over the free-space RF communication path1096, the waveguide RF communication path 98, and/or the dielectric RFcommunication path 1100. In this embodiment, the RF bus controller 1088further functions to select one of the waveguide RF communication path1098, the dielectric layer RF communication path 1100, or the free spaceRF communication path 1096 based on at least one aspect of one of theintra-device RF communications. For example, high data rate and/ornon-error tolerant communications (e.g., operating system levelcommunications) may occur over the waveguide RF communication path 1098,while lower data rate and/or error tolerant communications (e.g., someportions of application level communications) may occur over thefree-space RF communication path 1096. As another example, the aspect onwhich the RF communication path is selected may be user defined,operating system level defined, and/or pre-programmed into the device.As yet another example, the aspect may correspond to the IC initiatingan intra-device RF communication and/or the IC receiving it. As afurther example, the aspect may correspond to the number of intra-deviceRF communications 1090 an IC currently has in progress.

FIG. 23 is a schematic block diagram of another embodiment of themillimeter wave interface 1080 that interfaces ICs 1084, 1086 andincludes the RF bus controller 1088. In this embodiment, IC 1084includes a processing module 1104 and the RF bus transceiver 1108 and IC1086 includes an asynchronous circuit module 106 and the RF bustransceiver 1110. The processing module 1104 may be a single processingdevice or a plurality of processing devices. Such a processing devicemay be a microprocessor, micro-controller, digital signal processor,microcomputer, central processing unit, field programmable gate array,programmable logic device, state machine, logic circuitry, analogcircuitry, digital circuitry, and/or any device that manipulates signals(analog and/or digital) based on hard coding of the circuitry and/oroperational instructions. The processing module may have an associatedmemory and/or memory element, which may be a single memory device, aplurality of memory devices, and/or embedded circuitry of the processingmodule. Such a memory device may be a read-only memory, random accessmemory, volatile memory, non-volatile memory, static memory, dynamicmemory, flash memory, cache memory, and/or any device that storesdigital information. Note that when the processing module implements oneor more of its functions via a state machine, analog circuitry, digitalcircuitry, and/or logic circuitry, the memory and/or memory elementstoring the corresponding operational instructions may be embeddedwithin, or external to, the circuitry comprising the state machine,analog circuitry, digital circuitry, and/or logic circuitry.

The asynchronous circuit module 1106 may be any type of circuit and/orprogram that provides data to and/or receives data from the processingmodule 1104 in an asynchronous manner that is unpredictable to theprocessing module 1106. Such a circuit and/or program may be a userinterface input/output (I/O), email application, security application,peripheral I/O circuit, etc.

In this embodiment, the asynchronous circuit module 1106 provides an RFinterrupt request communication 1112 via the RF bus transceiver 1110 tothe RF bus transceiver 1108 coupled to the processing module 1104. TheRF interrupt request communication 1112 includes an interrupt requestthat is requesting the processing module 1104 to stop what it iscurrently doing and execute software to process the asynchronous circuitmodule's request. In response to receiving and/or commencing executionof the interrupt request, the processing module 1104 generates aninterrupt acknowledgement. The RF bus transceiver 1108 converts theinterrupt acknowledgement into an RF interrupt acknowledgementcommunication 1114.

The RF bus transceiver 1110 receives the RF interrupt acknowledgementcommunication 1114 and recaptures the interrupt acknowledgementtherefrom. The RF bus transceiver 1110 provides the interruptacknowledgement to the asynchronous circuit module 1106.

FIG. 24 is a schematic block diagram of another embodiment of themillimeter wave interface 1080 that interfaces the ICs 1084, 1086 andincludes the RF bus controller 1088. In this embodiment, the RF buscontroller 1088 receives RF bus requests 1122 from the ICs 1084, 1086via a wireline serial link 1120. The RF bus controller 1088 processesthe RF bus requests 1122 to produce RF bus grants 1124, which areprovided to the ICs 1084, 1086 via the wireline serial link 1120. Assuch, for the ICs 1084, 1086 to access an RF bus to support theintra-device RF communications 1090, the ICs 1084, 1086 communicate withthe RF bus controller 1088 via the wireline serial link 1120.

FIG. 25 is a schematic block diagram of another embodiment of themillimeter wave interface 1080 that interfaces the ICs 1084, 1086 andincludes the RF bus controller 1088. In this embodiment, the RF buscontroller 1088 receives RF bus requests 1122 from the ICs 1084, 1086via a wireless interface. The RF bus controller 1088 processes the RFbus requests 1122 to produce RF bus grants 1124, which are provided tothe ICs 1084, 1086 via the wireless interface. The RF bus request 1122and the RF bus grant 1124 may be transceived at one carrier frequencywhile the intra-device RF communications 1090 may be transceived at adifferent carrier frequency or different carrier frequencies.Alternatively, the RF bus request 1122 and the RF bus grant 1124 may betransceived at the carrier frequency or frequencies as the intra-deviceRF communications 1090.

FIG. 26 is a schematic block diagram of another embodiment of themillimeter wave interface 1080 that interfaces the ICs 1084, 1086 andincludes the RF bus controller 1088. In this embodiment, the RF buscontroller 1088 includes an RF bus transceiver 1130, IC 1084 includes acircuit module 1132 and the RF bus transceiver 1108, and IC 1086includes a circuit module 1134 and the RF bus transceiver 1110. Thecircuit modules 1132, 1134 may be any type of digital circuit, analogcircuit, logic circuit, and/or processing circuit. For example, one ofthe circuit modules 1132, 1134 may be, but is not limited to, amicroprocessor, a component of a microprocessor, cache memory, read onlymemory, random access memory, programmable logic, digital signalprocessor, logic gate, amplifier, multiplier, adder, multiplexer, etc.

In this embodiment, the inter-device RF communication 1090, RF busrequests 1122, and the RF bus grants 1124 occur within the samefrequency spectrum. To minimize interference between the obtainingaccess to the RF bus and using the RF bus for the inter-device RFcommunications 1090, the bus controller 1088 controls access to thefrequency spectrum by allocating at least one communication slot perframe to the wireless interface and allocating at least one othercommunication slot per frame for the intra-device RF communications. Thecommunication slots may be time division multiple access (TDMA) slotswithin a TDMA frame, frequency division multiple access (FDMA) slots ofan FDMA frame, and/or code division multiple access (CDMA) slots of aCDMA frame. Note that in this embodiment, frame is equivalent to apacket.

FIG. 27 is a diagram of an example of a frame of obtaining access to anRF Bus and using the RF bus by the embodiment of FIG. 26. The frame, orpacket, includes a controller inquiry field 1140, an IC response controlfield or fields 1142, a resource allocation field or fields 1144, and adata field or fields 1146. The RF bus controller uses the controllerinquiry field 1140 to determine whether one or more ICs have anup-coming need to access the RF bus. In one embodiment, the RF buscontroller 1088 addresses a single IC per frame as to whether the IC hasan up-coming need for the RF bus. In another embodiment, the RF buscontroller 1088 addresses two or more ICs as to whether they have anup-coming need for the RF bus. The RF bus controller 1088 may be use apolling mechanism to address the ICs, which indicates how and when toresponse to the polling inquiry.

The ICs 1084, 1086 respond to the RF bus controller's query in the ICresponse control field or fields 1142. In one embodiment, the ICs sharea single IC response control field using a carrier sense multiple access(CSMA) with collision avoidance technique, using pre-assigned sub-slots,using a round robin technique, using a poll-respond technique, etc. Inanother embodiment, the ICs have their own IC response control field1142. In either embodiment, the ICs 1084, 1086 response includes anindication of whether it has data to convey via the RF bus, how muchdata to convey, the nature of the data (e.g., application data,application instructions, operating system level data and/orinstructions, etc.), the target or targets of the data, a priority levelof the requester, a priority level of the data, data integrityrequirements, and/or any other information relating to the conveyance ofthe data via the RF bus.

The RF bus controller 1088 uses the resource allocation field or fields1144 to grant access to the RF bus to one or more ICs 1084, 1086. In oneembodiment, the RF bus controller 1088 uses a single field to respond toone or more ICs. In another embodiment, the RF bus controller 1088responds to the ICs in separate resource allocation fields 1144. Ineither embodiment, the RF bus grant 1144 indicates when, how, and forhow long the IC has access to the RF bus during the one or more datafields 1146. Various embodiments of requesting and obtaining access tothe RF bus and transceiving via the RF bus will be described in greaterdetail with reference to FIGS. 65-79.

FIG. 28 is a schematic block diagram of another embodiment of themillimeter wave interface 1080 that interfaces the ICs 1084, 1086 andincludes the RF bus controller 1088. In this embodiment, the RF buscontroller 1088 includes an RF bus transceiver 1130. IC 1084 includesthe circuit module 132 the RF bus transceiver 1108, and an RFtransceiver 1160. IC 1086 includes the circuit module 1134, the RF bustransceiver 1110, and an RF transceiver 1152.

In this embodiment, the inter-device RF communications 1090 occur in adifferent frequency spectrum than the RF bus requests 1122 and the RFbus grants 1124. As such, they can occur simultaneously with minimalinterference. In this manner, the RF bus requests 1122 and RF bus grants1124 may be communicated using a CSMA with collision avoidancetechnique, a poll-response technique, allocated time slots of a TDMAframe, allocated frequency slots of an FDMA frame, and/or allocated codeslots of a CDMA frame in one frequency spectrum or using one carrierfrequency and the inter-device RF communications 1090 may use a CSMAwith collision avoidance technique, a poll-response technique, allocatedtime slots of a TDMA frame, allocated frequency slots of an FDMA frame,and/or allocated code slots of a CDMA frame in another frequencyspectrum or using another carrier frequency.

FIG. 29 is a schematic block diagram of another embodiment of themillimeter wave interface 1080 that interfaces a plurality of integratedcircuits (ICs) 1160, 1162, and includes the RF bus controller 1088, andan RF bus 1190. Each of the ICs 1160, 1162 includes a plurality ofcircuit modules 1170-1176 and each of the circuit modules 1170-1176includes a radio frequency (RF) bus transceiver 1180-1186. The circuitmodules 1170-1176 may be any type of digital circuit, analog circuit,logic circuit, and/or processing circuit that can be implemented on anIC. For example, one of the circuit modules 1170-1176 may be, but is notlimited to, a microprocessor, a component of a microprocessor, cachememory, read only memory, random access memory, programmable logic,digital signal processor, logic gate, amplifier, multiplier, adder,multiplexer, etc.

In this embodiment, the RF bus controller 1088, which may be a separateIC or contained with one of the ICs 1160-1162, controls intra-IC RFcommunications 1192 between circuit modules 1170-1176 of different ICs1160, 1162 and controls inter-IC RF communications 1194 between circuitmodules 1170-1172 or 1174-1176 of the same IC. In this manner, at leastsome of the communication between ICs and between circuit modules of anIC is done wirelessly via the RF bus transceivers 180-186. Note that thecircuit modules 1170-1172 may also be inter-coupled with one or moretraces within the IC 1160, the circuit modules 1174-1176 may also beinter-coupled with one or more traces within the IC 1162, and that IC1160 may be coupled to IC 1162 via one or more traces on a supportingsubstrate (e.g., a printed circuit board).

The intra-IC RF communications 1192 and the inter-IC RF communications1194 may be RF data communications, RF instruction communications, RFcontrol signal communications, and/or RF input/output communications.For example, data, control, operational instructions, and/orinput/output communications (e.g., analog input signals, analog outputsignals, digital input signals, digital output signals) that aretraditionally conveyed between ICs via traces on a printed circuit boardare at least partially transmitted by the RF bus transceivers 1180-1186via the RF bus 1190.

The intra-IC RF communications 1192 and/or the inter-IC RFcommunications 1194 may also include operating system levelcommunications and application level communications. The operatingsystem level communications are communications that correspond toresource management of the millimeter wave interface 1080 loading andexecuting applications (e.g., a program or algorithm), multitasking ofapplications, protection between applications, device start-up,interfacing with a user of the device, etc. The application levelcommunications are communications that correspond to the data conveyed,operational instructions conveyed, and/or control signals conveyedduring execution of an application.

The RF bus 1190 may be one or more of a free-space RF communication path1096, a waveguide RF communication path 1098, and/or a dielectric RFcommunication path 1100. For example, the RF bus 1190 may include atleast one data RF bus, at least one instruction RF bus, and at least onecontrol RF bus for intra-IC RF communications 1192 and the inter-IC RFcommunications 1194. In this example, intra-IC RF data communications1192 may occur over a free-space RF communication path 1096, while theintra-IC RF instruction and/or control communications 1192 may occurover a waveguide RF communication path 1098 and/or a dielectric RFcommunication path 1100 within the IC 160 or 162. Further, inter-IC RFdata communications 1194 may occur over a free-space RF communicationpath 1096, while the intra-IC RF instruction and/or controlcommunications 1194 may occur over a waveguide RF communication path 98and/or a dielectric RF communication path 1100 within a supportingsubstrate of the ICs 1160-1162. As an alternative example, the inter-and intra-IC communications 1192-1194 may occur over multiple waveguideRF communication paths, multiple dielectric RF communication paths,and/or multiple free-space RF communication paths (e.g., use differentcarrier frequencies, distributed frequency patterns, TDMA, FDMA, CDMA,etc.).

FIG. 30 is a schematic block diagram of another embodiment of themillimeter wave interface 1080 that interfaces a plurality of integratedcircuits (ICs) 1160, 1162, and includes the RF bus controller 1088, aplurality of inter-IC RF buses 196, and an intra-IC RF bus 198. Each ofthe ICs 1160, 1162 includes a plurality of circuit modules 1170-1176 anda serial interface module 200-202. Each of the circuit modules 1170-1176includes a radio frequency (RF) bus transceiver 1180-1186.

In this embodiment, the RF bus controller 1088 is coupled to the ICs1160-1162 via a wireline serial link 204 to control access to theinter-IC RF buses 1196 and to the intra-IC RF bus 1198. For instance,when a circuit module 1170-1176 has data to transmit to another circuitmodule 1170-1176 of the same IC or of a different IC, the requestingcircuit module 1170-1176 provides an RF bus request to the RF buscontroller 1088 via the wireline serial link 204 and the correspondingserial interface module 200-202. The serial link 204 and thecorresponding serial interface modules 200-202 may be a standardizedprotocol, a de-facto standard protocol, or a proprietary protocol. Forexample, the serial link 204 may be a universal serial bus (USB), anIEEE 1394 link, an I2C link, an I2S link, etc.

The RF bus controller 1088 processes the RF bus request, as will bedescribed in greater detail with reference to FIGS. 65-69, to determineat least one of whether the requestor needs access to one of theplurality of inter-IC RF buses 1196 or to the intra-IC RF bus 1198, howmuch data it has to send, the type of the data, the location of thetarget circuit module(s), the priority of the requester, the priority ofthe data, etc. When the RF bus controller 1088 has determined how andwhen the requestor is to access the RF bus 1196 and/or 1198, the RF buscontroller 1088 provides an RF bus grant to the requestor via thewireline link 204.

As shown, the intra-IC RF bus 1198 supports intra-IC RF communications1194 and the plurality of inter-IC RF buses 196 support correspondinginter-IC RF communications 1192. In this manner, multiple inter-IC RFcommunications 192 may be simultaneously occurring and may also occursimultaneously with one or more intra-IC RF communications 1194.

FIG. 31 is a schematic block diagram of another embodiment of themillimeter wave interface 1080 that interfaces a plurality of integratedcircuits (ICs) 1160, 1162, and includes the RF bus controller 1088, aplurality of inter-IC RF buses 1196, and an intra-IC RF bus 1198. Eachof the ICs 1160, 1162 includes a plurality of circuit modules 1170-1176and an RF transceiver 210-212. Each of the circuit modules 1170-1176includes a radio frequency (RF) bus transceiver 1180-1186 and the RF buscontroller 1088 includes the RF bus transceiver 1130.

In this embodiment, the RF bus controller 1088 is coupled to the ICs1160-1162 via a wireless link 214 to control access to the inter-IC RFbuses 196 and to the intra-IC RF bus 1198. For instance, when a circuitmodule 1170-1176 has data to transmit to another circuit module1170-1176 of the same IC or of a different IC, the requesting circuitmodule 1170-1176 provides an RF bus request to the RF bus controller1088 via the wireless link 214 and the RF transceiver 210-212. Thewireless link 214 and the corresponding RF transceivers 210-212 may be astandardized protocol, a de-facto standard protocol, or a proprietaryprotocol.

The RF bus controller 1088 processes the RF bus request, as will bedescribed in greater detail with reference to FIGS. 65-69, to determineat least one of whether the requester needs access to one of theplurality of inter-IC RF buses 1196 or to the intra-IC RF bus 1198, howmuch data it has to send, the type of the data, the location of thetarget circuit module(s), the priority of the requester, the priority ofthe data, etc. When the RF bus controller 1088 has determined how andwhen the requestor is to access the RF bus 1196 and/or 1198, the RF buscontroller 1088 provides an RF bus grant to the requester via thewireless link 214.

In one embodiment, the RF bus transceiver 1130 operates within a firstfrequency band and the intra-IC RF communications 192 and the inter-ICRF communications 1194 occur within the first frequency band. In thisinstance, the RF bus controller 1088 allocates at least onecommunication slot to the wireless interface link 214, allocates atleast one other communication slot for the intra-IC RF communications1192, and allocates at least another communication slot for the inter-ICRF communications 1194. The communication slots may be time divisionmultiple access (TDMA) slots, frequency division multiple access (FDMA)slot, and/or code division multiple access (CDMA) slots.

In another embodiment, the RF bus transceiver 1130 operates within afirst frequency band, the intra-IC RF communications 1192 occur withinthe first frequency band, and the inter-IC RF communications 1194 occurwithin a second frequency band. In this instance, the RF bus controller1088 allocates at least one communication slot in the first frequencyband to the wireless link 214 and allocates at least one othercommunication slot in the first frequency band for the intra-IC RFcommunications 192. The communication slots may be time divisionmultiple access (TDMA) slots, frequency division multiple access (FDMA)slot, and/or code division multiple access (CDMA) slots.

In another embodiment, the RF bus transceiver 1130 operates within afirst frequency band, the inter-IC RF communications 1194 occur withinthe second frequency band, and the intra-IC RF communications 1192 occurwithin the frequency band. In this instance, the RF bus controller 1088allocates at least one communication slot in the second frequency bandto the wireless link 214 and allocates at least one other communicationslot in the second frequency band for the inter-IC RF communications194. The communication slots may be time division multiple access (TDMA)slots, frequency division multiple access (FDMA) slot, and/or codedivision multiple access (CDMA) slots.

In another embodiment, the RF bus transceiver 1130 operates within afirst frequency band, the intra-IC RF communications 1192 occur withinthe second frequency band, and the inter-IC RF communications 1194 occurwithin a third frequency band. With the different types of communication(e.g., RF bus access, inter-IC, and intra-IC) occurring within differentfrequency bands, the different types of communication may occursimultaneously with minimal interference from each other.

FIG. 32 is a schematic block diagram of another embodiment of themillimeter wave interface 1080 that includes the RF bus controller 1088,a processing core 220, a memory system 222, a peripheral interfacemodule 224, a plurality of peripheral circuits 228-230, an RF memory bus242, and an RF I/O bus 244. Each of the processing core 220, the memorysystem 222, the peripheral interface module 224, and the plurality ofperipheral circuits 228-230 includes one or more RF bus transceivers232-240. The plurality of peripheral circuits 228-230 includes two ormore of a hard disk drive, a compact disk (CD) drive, a digital videodisk (DVD) drive, a video card, an audio card, a wireline network card,a wireless network card, a universal subscriber identity module (USIM)interface and/or security identification module (SIM) card, a USBinterface, a display interface, a secure digital input/output (SDIO)interface and/or secure digital (SD) card or multi-media card (MMC), acoprocessor interface and/or coprocessor, a wireless local area network(WLAN) interface and/or WLAN transceiver, a Bluetooth interface and/orBluetooth transceiver, a frequency modulation (FM) interface and/or FMtuner, a keyboard interface and/or keyboard, a speaker interface and/ora speaker, a microphone interface and/or a microphone, a globalpositioning system (GPS) interface and/or a GPS receiver, a camerainterface and/or an image sensor, a camcorder interface and/or a videosensor, a television (TV) interface and/or a TV tuner, a UniversalAsynchronous Receiver-Transmitter (UART) interface, a Serial PeripheralInterface (SPI) interface, a pulse code modulation (PCM) interface, etc.

In this embodiment, the peripheral interface module 224 includes a firstRF bus transceiver 236 and a second RF bus transceiver 238. The first RFbus transceiver 236 communicates via the RF memory bus 242 and thesecond RF bus transceiver communicates via the RF I/O bus 244. In thisinstance, the peripheral interface module 224 functions as an interfacefor one of the plurality of peripheral circuits 228-230 to communicatewith the processing core 220 and/or the memory system 222 via the RFmemory bus 242.

The RF bus controller 1088, which may be coupled to the processing core220, the memory system 222 and the peripheral interface module 224 via awireline serial link and/or a wireless link, controls access to the RFinput/output bus 244 among the plurality of peripheral circuits 228-230and the peripheral interface module 224 and controls access to the RFmemory bus 242 among the processing core 220, the memory system 222, andthe peripheral interface module 224. Note that the RF input/output bus244 supports at least one of: RF peripheral data communications, RFperipheral instruction communications, and RF peripheral control signalcommunications, where the RF peripheral control signal communicationsincludes an RF interrupt request communication, and/or an RF interruptacknowledgement communication.

The RF memory bus 242 supports at least one of: RF memory datacommunications, RF memory instruction communications, and RF memorycontrol signal communications. The RF memory bus may further support RFoperating system level communications and RF application levelcommunications.

FIG. 33 is a schematic block diagram of an embodiment of an RFtransceiver device that includes a processing module 250, memory 252, abaseband processing module 254, an RF section 256, the RF bus controller1088 and an RF bus 262. The processing module 250 includes a processingmodule RF bus transceiver 258 and the memory includes a memory RF bustransceiver 260. The processing module 250 and the baseband processingmodule 254 may be the same processing module or different processingmodules, where a processing module may be a single processing device ora plurality of processing devices. Such a processing device may be amicroprocessor, micro-controller, digital signal processor,microcomputer, central processing unit, field programmable gate array,programmable logic device, state machine, logic circuitry, analogcircuitry, digital circuitry, and/or any device that manipulates signals(analog and/or digital) based on hard coding of the circuitry and/oroperational instructions. The processing module may have an associatedmemory and/or memory element (e.g., memory 252), which may be a singlememory device, a plurality of memory devices, and/or embedded circuitryof the processing module. Such a memory device may be a read-onlymemory, random access memory, volatile memory, non-volatile memory,static memory, dynamic memory, flash memory, cache memory, and/or anydevice that stores digital information. Note that when the processingmodule implements one or more of its functions via a state machine,analog circuitry, digital circuitry, and/or logic circuitry, the memoryand/or memory element storing the corresponding operational instructionsmay be embedded within, or external to, the circuitry comprising thestate machine, analog circuitry, digital circuitry, and/or logiccircuitry. Further note that, the memory element stores, and theprocessing module executes, hard coded and/or operational instructionscorresponding to at least some of the steps and/or functions illustratedin FIGS. 33-41.

The baseband processing module 254 is coupled to convert outbound data264 into an outbound symbol stream 266. This may be done in accordancewith one or more wireless communication protocols including, but notlimited to, IEEE 802.11, Bluetooth, GSM, RFID, CDMA, Enhanced Data ratesfor GSM Evolution (EDGE), General Packet Radio Service (GPRS), newand/or current versions thereof, modifications thereof, extensionsthereof, combinations thereof, new WLAN standards, new cellular voiceand/or data standards, and/or new wireless personal area networks(WPAN).

The RF section 256 converts the outbound symbol stream 266 into anoutbound RF signal 268. In an embodiment, the RF section 256 includes adigital to analog conversion module, an up-conversion module, and apower amplifier module. The digital to analog conversion module convertsthe outbound symbol stream 266 into an analog symbol stream. Theup-conversion module, which may be a direct conversion module or asuperheterodyne module, mixes the analog symbol stream with a localoscillation to produce an up-converted signal. The power amplifiermodule amplifies the up-converted signal to produce the outbound RFsignal 268. In another embodiment, the up-conversion module modulatesphase of the local oscillation based on phase information of the analogsymbol stream to produce the up-converted signal. The power amplifiermodule amplifies the up-converted signal based on a constant amplifierfactor or based on amplitude modulation information of the analog symbolstream to produce the outbound RF signal 268.

The RF section 256 is also coupled to and to convert an inbound RFsignal 270 into an inbound symbol stream 272. In one embodiment, the RFsection 256 includes a low noise amplifier module, a down-conversionmodule, and an analog to digital conversion module. The low noiseamplifier module amplifies the inbound RF signal 270 to produce anamplified inbound RF signal. The down conversion module, which may adirection conversion module or a superheterodyne module, mixes theamplified inbound RF signal with a local oscillation to produce ananalog inbound symbol stream. The analog to digital conversion moduleconverts the analog inbound symbol stream into the inbound symbol stream272.

The baseband processing module 254 is also coupled to convert theinbound symbol stream 272 into inbound data 274. This may be done inaccordance with one or more wireless communication protocols including,but not limited to, IEEE 802.11, Bluetooth, GSM, RFID, CDMA, EnhancedData rates for GSM Evolution (EDGE), General Packet Radio Service(GPRS), new and/or current versions thereof, modifications thereof,extensions thereof, combinations thereof, new WLAN standards, newcellular voice and/or data standards, and/or new wireless personal areanetworks (WPAN). Note that the inbound and outbound data 264, 274 may bevoice signals, audio signals, video signals, text signals, graphicssignals, short messaging signals, cellular data signals, etc.

The RF bus controller 1088 is coupled to control access to the RF bus262, which may include one or more waveguide RF communication paths, oneor more dielectric RF communication paths, and/or one or more free-spaceRF communication paths. In one embodiment, the processing module 250generates the outbound data 264, which is converted into an RF busoutbound data signal 278 by the RF bus transceiver 258. The RF buscontroller 1088 controls conveyance of the RF bus outbound data signal278 on the RF bus 262. In another embodiment, the memory 252 providesthe outbound data 264, which is converted into the RF bus outbound datasignal 278 by the RF bus transceiver 260.

The RF bus controller 1088 further functions to control access to the RFbus 262 for providing the inbound data 274 as an RF bus inbound datasignal 276 to the processing module RF bus transceiver 258 or to thememory RF bus transceiver 260. Note that in an embodiment of the RFtransceiver device, the baseband processing module 254 is coupled to theRF section 256 via a wireless digital-RF interface.

FIG. 34 is a schematic block diagram of an embodiment of an RFtransceiver device that includes a processing module 250, memory 252, abaseband processing module 254, an RF section 256, the RF bus controller1088 and an RF bus 262. The processing module 250 includes a processingmodule RF bus transceiver 258 and the memory includes a memory RF bustransceiver 260. In this embodiment, the baseband processing module 254includes an RF bus transceiver 280, which converts the inbound data 274into the RF bus inbound data signal 276 and converts the RF bus outbounddata signal 278 into the outbound data 264.

FIG. 35 is a schematic block diagram of an embodiment of an RFtransceiver device that includes a processing module 250, memory 252, abaseband processing module 254, an RF section 256, the RF bus controller1088 and an RF bus 262. The processing module 250 includes a processingmodule RF bus transceiver 258 and the memory includes a memory RF bustransceiver 260. In this embodiment, the RF section 256 receives the RFbus outbound data signal 278 and converts it into a baseband (BB) ornear baseband outbound data signal 290, which has a carrier frequency of0 Hz to a few MHz. Note that the RF section 256 may be coupled tomultiple antennas (as shown) or may be coupled to a single antenna.

The baseband processing module 254 converts the baseband or nearbaseband outbound data signal 290 into the outbound data 264 inaccordance with a standardized wireless communication protocol (e.g.,GSM, EDGE, GPRS, CDMA, IEEE 802.11 Bluetooth), a modified standardwireless communication protocol (e.g., a modified version of GSM, EDGE,GPRS, CDMA, IEEE 802.11 Bluetooth), or a proprietary wirelesscommunication protocol (e.g., non-return to zero encode/decode, bi-phaseencode/decode). The baseband processing module 254 then converts theoutbound data 264 into the outbound symbol stream 266, which isconverted into the outbound RF signal 268 by the RF section 256.

The RF section 256 receives the inbound RF signal 270 and converts itinto the inbound symbol stream 272. The baseband processing module 254converts the inbound symbol stream 272 into the inbound data 274 andthen converts the inbound data 274 into a baseband or near basebandinbound data signal 292. The RF section 256 converts the baseband ornear baseband inbound data signal 292 into the RF bus inbound datasignal 276. Note that in an embodiment the baseband processing moduleconverts the outbound data 264 into the outbound symbol stream 266 andconverts the inbound symbol stream 272 into the inbound data 274 inaccordance with one or more of a wireless personal area network (WPAN)protocol (e.g., Bluetooth), a wireless local area network (WLAN)protocol (e.g., IEEE 802.11), a cellular telephone voice protocol (e.g.,GSM, CDMA), a cellular telephone data protocol (e.g., EDGE, GPRS), anaudio broadcast protocol (e.g., AM/FM radio), and a video broadcastprotocol (e.g., television).

In the various embodiments of an RF transceiver device as discussed withreference to FIGS. 33-35, the inbound and outbound RF signals 268 and270 may be in the same frequency band or a different frequency band thanthe RF bus inbound and outbound data signals 276 and 278. For example,the inbound and outbound RF signals 268 and 270 may have a carrierfrequency in a 2.4 GHz or 5 GHz frequency band while the RF bus inboundand outbound data signals 276 and 278 may have a carrier frequency in a60 GHz frequency band. As another example, the inbound and outbound RFsignals 268 and 270 and the RF bus inbound and outbound data signals 276and 278 may have a carrier frequency in a 60 GHz frequency band. Whenthe signals 268, 270, 276, and 278 are in the same frequency band, thefrequency band may be shared to minimize interference between thedifferent signals.

FIG. 36 is a diagram of an example of a frame of an RF transceiverdevice wireless communication that shares a frequency band and minimizesinterference between the different signals 268, 270, 276, and 278. Inthis example, the frame includes an inbound RF signal slot 300, an RFbus inbound data signal slot 302, an RF bus outbound data signal 304,and an outbound RF signal 306. The slots 300-306 may be TDMA slots, CDMAslots, or FDMA slots, which may be reallocated on a frame by frame basisby the RF bus controller 1088. For example, the processing module 250and/or the baseband processing module 254 may request one or more slotsfrom the RF bus controller 1088 for the inbound RF signal 270, theoutbound RF signal 268, the RF bus inbound data signal 276, and/or theRF bus outbound data signal 278. Note that the frame may include anadditional slot for bus access communications if the RF bus requests andRF bus grants are communicated wirelessly within the same frequency bandas the signals 268, 270, 276, and 278.

FIG. 37 is a logic diagram of an embodiment of a method of resourceallocation for an intra-device wireless communication that begins atstep 310 where the processing module 250 and/or the baseband processingmodule 254 determine a potential overlapping of one of the RF businbound data signal 276 and the RF bus outbound data signal 278 with oneof the inbound RF signal 270 and the outbound RF signal 268. In thisembodiment, the signals 268, 270, 276, and 278 may be transmitted and/orreceived at any time without a structured ordering of the signals (inother words, the signals do not have allocated slots). If a potentialoverlap is not detected (i.e., the transmission or reception of onesignal will not interfere with the transmission or reception of anothersignal), the process proceeds to step 312 where the RF bus communication(e.g., the RF bus inbound or outbound data signal 276 or 278) or theinbound or outbound RF signal 270 or 268 is transmitted or received.

If a potential overlap is detected, the process proceeds to step 314where the frequency and/or phase of the RF bus inbound data signal 276and/or of the RF bus outbound data signal 278 is adjusted. For example,if a potential overlap is detected, the phase of the RF buscommunications (e.g., signals 276 or 278) may be adjusted to beorthogonal with the inbound or outbound RF signals 270 or 268 therebysubstantially reducing the received signal strength of the orthogonalsignal. As another example, the carrier frequency may be adjusted by afrequency offset such that it has a different carrier frequency than theinbound or outbound RF signal 270 or 268.

The process then proceeds to step 316 where blocking of the inbound RFsignal 270 or the outbound RF signal 268 for the RF bus communication isenabled. As such, by adjusting the phase and/or frequency of the RF buscommunication, the inbound or outbound RF signal 270 or 268 may betreated as an interferer with respect to the RF bus communications thatcan be substantially blocked. Thus, if a potential overlap exists, theRF bus communications are adjusted such that they experience acceptablelevels of interference from the inbound or outbound RF signals.

FIG. 38 is a diagram of another example of a frame of an RF transceiverdevice wireless communication that shares a frequency band and minimizesinterference between the different signals 268, 270, 276, and 278. Inthis example, the frame includes the inbound RF signal slot 300; anoutbound RF signal, an RF bus inbound data signal, or composite signalslot 320, and the RF bus outbound data signal 304. The slots 300, 320,and 304 may be TDMA slots, CDMA slots, or FDMA slots, which may bereallocated on a frame by frame basis by the RF bus controller 1088.Note that the frame may include an additional slot for bus accesscommunications if the RF bus requests and RF bus grants are communicatedwirelessly within the same frequency band as the signals 268, 270, 276,and 278.

In this example, the baseband processing module 254 processes the datafor the outbound RF signal 268 and the RF bus inbound data signal 276.As such, the baseband processing module 254 has knowledge of whichsignal it is processing and thus can request allocation of a resourcefor the appropriate signal (e.g., 268 or 276). In addition, the basebandprocessing module 254 may simultaneously process the data for theoutbound RF signal 268 and the RF bus inbound data signal 276 via acomposite signal.

FIG. 39 is a diagram of an example of mapping data of an RF transceiverdevice wireless communication into a composite signal. In this example,the baseband processing module 254 combines bits 322 of the outbounddata 264 and bits 324 of the inbound data 274 to produce composite data.In this example, the bits 322 of the outbound data 264 are leastsignificant bits of the composite data and the bits 324 of the inbounddata 274 are most significant bits of the composite data. The basebandprocessing module then encodes the composite data to produce encodeddata; interleaves the encoded data to produce interleaved data; maps theinterleaved data to produce mapped data; and converts the mapped datafrom the frequency domain to the time domain to produce a baseband ornear baseband composite outbound data signal. The RF section 256converts the baseband or near baseband composite outbound data signalinto a composite outbound RF signal, wherein the composite outbound RFsignal includes the outbound RF signal 268 and the RF bus inbound datasignal 276.

The RF bus transceiver 258 or 260 receives the composite outbound RFsignal, converts it into the baseband or near baseband compositeoutbound data signal. A baseband processing module within the RF bustransceiver 258 or 260 converts the baseband or near baseband compositeoutbound data signal from the time domain to the frequency domain toproduce the mapped data; demaps the mapped data to produce interleaveddata; deinterleaves the interleaved data to produce encoded data; anddecodes the encoded data to produce the inbound data 274 and outbounddata 264. The RF bus transceiver 258 or 260 is programmed to ignore theoutbound data 264 bits of the composite data such that the resultingrecovered data from the composite outbound RF signal is the inbound data274.

An RF transceiver within the target of the outbound RF signal 268 treatsthe composite outbound RF signal as a lower mapped rate outbound RFsignal. As shown, the composite data is mapped using a 16 QAM(quadrature amplitude mapping scheme). A first quadrant has mapped bitsof 0000, 0001, 0010, and 0011; a second quadrant has mapped bits of0100, 0101, 0110, and 0111; a third quadrant has mapped bits of 1100,1101, 1110, and 1111; and a fourth quadrant has mapped bits of 1000,1001, 1010, and 1011. If the RF transceiver within the target uses aQPSK (quadrature phase shift keying), if the composite signal is withinthe first quadrant, the RF transceiver will interpret this as a mappedvalue of 00, if the composite signal is within the second quadrant, theRF transceiver will interpret this as a mapped value of 01, if thecomposite signal is within the third quadrant, the RF transceiver willinterpret this as a mapped value of 11, and if the composite signal iswithin the fourth quadrant, the RF transceiver will interpret this as amapped value of 10.

In general, since the RF bus transceivers should experiencesignificantly greater signal integrity than the RF transceiver withinthe target, the RF bus transceivers can operate at a higher mapping ratethan the RF transcevier within the target. As such, the basebandprocessing module may convert the bits 322 of the outbound data 264 andthe bits 324 of the inbound data 274 into the baseband or near basebandcomposite outbound data signal using one of N-QAM (quadrature amplitudemodulation) and N-PSK (phase shift keying), wherein N equals 2^(x) and xequals the number of bits of the outbound data 264 plus the number ofbits of the inbound data 274.

FIG. 40 is a schematic block diagram of another embodiment of an RFtransceiver device that includes a processing module 250, memory 252, abaseband processing module 254, an RF section 256, the RF bus controller1088, an RF bus 262, a peripheral interface module 224, an RF I/O bus244, and a plurality of peripheral circuits 228-230. Each of theprocessing module 250, the memory 242, the peripheral interface module224, and the peripheral circuits 228-230 includes at least one RF bustransceiver 235, 236, 238, 240, 258, and 260.

In this embodiment, the RF bus controller 1088 controls access to the RFbus 262 for providing the RF bus outbound data signal 278 from one ofthe processing module RF bus transceiver 258, the memory RF bustransceiver 260, and the peripheral interface RF bus transceiver 236.The RF bus controller 1088 also controls access to the RF bus 262 forproviding the RF bus inbound data signal 276 to one of the processingmodule RF bus transceiver 258, the memory RF bus transceiver 260, andthe peripheral interface RF bus transceiver 236.

The RF bus controller 1088 further controls access to a peripheral I/ORF bus 244 among a plurality of peripheral circuits 228-230. In anembodiment, when access is granted to one of the plurality of peripheralcircuits 228-230, it provides an inbound RF peripheral data signal tothe peripheral interface RF bus transceiver 238 or receives an outboundRF peripheral data signal from the peripheral interface RF bustransceiver 238. The inbound or outbound RF peripheral data signal maydata from the processing module 250, may be data from the memory 252,may be the RF bus inbound data signal 276, may be the RF bus outbounddata signal 278, may the inbound data 274, and/or may be the outbounddata 264.

FIG. 41 is a schematic block diagram of another embodiment of an RFtransceiver device that includes a processing module 330, memory 332, abaseband processing module 254, an RF section 256, the RF bus controller1088, a bus structure 334, a peripheral interface module 224, anexternal RF bus 336, and a plurality of peripheral circuits 228-230.Each of the peripheral interface module 224 and the peripheral circuits228-230 includes at least one RF bus transceiver 235, 238, and 240. Theprocessing module 330 and the baseband processing module 254 may be thesame processing module or different processing modules, where aprocessing module may be a single processing device or a plurality ofprocessing devices. Such a processing device may be a microprocessor,micro-controller, digital signal processor, microcomputer, centralprocessing unit, field programmable gate array, programmable logicdevice, state machine, logic circuitry, analog circuitry, digitalcircuitry, and/or any device that manipulates signals (analog and/ordigital) based on hard coding of the circuitry and/or operationalinstructions. The processing module may have an associated memory and/ormemory element (e.g., memory 332), which may be a single memory device,a plurality of memory devices, and/or embedded circuitry of theprocessing module. Such a memory device may be a read-only memory,random access memory, volatile memory, non-volatile memory, staticmemory, dynamic memory, flash memory, cache memory, and/or any devicethat stores digital information. Note that when the processing moduleimplements one or more of its functions via a state machine, analogcircuitry, digital circuitry, and/or logic circuitry, the memory and/ormemory element storing the corresponding operational instructions may beembedded within, or external to, the circuitry comprising the statemachine, analog circuitry, digital circuitry, and/or logic circuitry.

In this embodiment, the processing module 330, the memory 332, thebaseband processing module 254, and the peripheral interface module 224are coupled together via a bus structure 334, which may be an advancedhigh-performance (AHB) bus matrix. As such, data between these modulesoccurs with the bus. The peripheral interface module 224 is coupled tothe plurality of peripheral circuits 228-230 via the external RF bus336, which may be one or more waveguide RF communication paths, one ormore dielectric RF communication paths, and/or one or more free-space RFcommunication paths.

In this instance, the RF bus controller 1088 controls access theexternal RF bus 336 among a plurality of peripheral circuits 228-230. Inan embodiment, when access is granted to one of the plurality ofperipheral circuits 228-230, it provides an inbound RF peripheral datasignal to the peripheral interface RF bus transceiver 238 or receives anoutbound RF peripheral data signal from the peripheral interface RF bustransceiver 238. The inbound or outbound RF peripheral data signal maydata from the processing module 330, may be data from the memory 332,may the inbound data 274, and/or may be the outbound data 264.

FIG. 42 is a schematic block diagram of another embodiment of a devicethat includes a plurality of integrated circuits (ICs) 500-502 and an RFbus structure 528. Each of the plurality of ICs 500-502 includes aplurality of circuit modules 504-506, 508-510, a switching module 512,514, an RF bus transceiver 516, 518, an antenna interface 520, 522, andan antenna structure 534, 526. The circuit modules 504-510 may be anytype of digital circuit, analog circuit, logic circuit, and/orprocessing circuit. For example, one of the circuit modules 504-510 maybe, but is not limited to, a microprocessor, a component of amicroprocessor, cache memory, read only memory, random access memory,programmable logic, digital signal processor, logic gate, amplifier,multiplier, adder, multiplexor, etc.

In this embodiment, the circuit modules 504-506 and 508-510 of an IC500, 502 share an RF bus transceiver 516, 518 for external ICcommunications (e.g., intra-device communications and/or inter-ICcommunications) and communicate via the switching module 512, 514 forinternal IC communications (e.g., intra-IC communications). Theswitching module 512, 514 may include a wireline bus structure (e.g.,AHB) and a plurality of switches, multiplexers, demultiplexers, gates,etc. to control access to the wireline bus structure and/or access tothe RF bus transceiver.

The antenna interface 520, 522 may include one or more of a transformerbalun, an impedance matching circuit, and a transmission line to providea desired impedance, frequency response, tuning, etc. for the antennastructure 524, 526. The antenna structure 524, 526 may be implemented asdescribed in co-pending patent application entitled AN INTEGRATEDCIRCUIT ANTENNA STRUCTURE, having a filing date of Dec. 29, 2006, and aSer. No. 11/648,826.

The RF bus structure 528, which may be one or more waveguide RFcommunication paths, one or more dielectric RF communication paths,and/or one or more free-space RF communication paths, receives outboundRF bus signal from the antenna structure 524, 526 and provides it to theantenna structure 524, 526 of another one of the plurality of ICs500-502.

In an embodiment, the switching module 512, 514 performs the method ofFIG. 43 to control internal IC communications and external ICcommunications. The method begins at step 530 where the switching module512, 514 receives an outbound bus communication from one of theplurality of circuit modules 504-510. The process then proceeds to step532 where the switching module 512, 514 determines whether the outboundbus communication is an internal IC communication or an external ICcommunication.

When the outbound bus communication is an internal IC communication, theprocess proceeds to step 534 where the switching module 512, 514provides the outbound bus communication to another one of the pluralityof circuit modules 504-506, 508-510. In this instance, the switchingmodule 512, 514 utilizes the wireline bus structure and the appropriateswitches, multiplexers, etc. to couple one circuit module 504 to theother 506 for the conveyance of the outbound bus communication.

When the outbound bus communication is an external IC communication, theswitching module 512, 514 outputs the outbound bus communication to theRF bus transceiver 516, 518, which converts the outbound buscommunication into an outbound RF bus signal. The antenna interface andthe antenna structure provide the outbound RF bus signal to the RF busstructure 528 for conveyance to another circuit module of another IC.

For an inbound RF bus signal, the antenna structure 524, 526 receivesthe inbound RF bus signal from the RF bus structure 528 and provides itto the RF bus transceiver 516, 518 via the antenna interface 520, 522.The RF bus transceiver 516, 518 converts the inbound RF bus signal intoan inbound bus communication. The switching module 512, 514 interpretsthe inbound bus communication and provides it to the addressed circuitmodule or modules.

FIG. 44 is a diagram of an embodiment of a device that includes theplurality of integrated circuits (ICs) 500-502, the RF bus structure528, and a supporting substrate 540. In this embodiment, each of the ICs500-502 includes a package substrate 548, 550, and a die 544, 546 andthe supporting substrate 540 supports the ICs 500-502 and includes asupporting substrate micro-electromechanical (MEM) area 542. Thesupporting substrate 540 may be printed circuit board with or withouttraces, a non-conductive plastic board, and/or any other type ofsubstrate that will support a plurality of ICs 500-502.

As shown, the RF bus structure 528 is within the supporting substrateMEM area 542 and includes channels to the antenna structures 524, 526 ofthe ICs 500-502. In this manner, RF bus transmissions by the antennastructures 524, 526 is substantially contained within the MEM area 542that contains the RF bus structure 528. As such, interference from otherRF communications should be minimized and the RF bus transmissionsshould have minimal interference on the other RF transmissions.

As is also shown, the package substrate 548, 550 includes a MEM area552, 554. In an embodiment, the antenna interface 520, 522 and theantenna structure 524, 526 are within the package substrate MEM area552, 554.

FIG. 45 is a diagram of an embodiment of a device that includes theplurality of integrated circuits (ICs) 500-502, the RF bus structure528, and the supporting substrate 540. In this embodiment, each of theICs 500-502 includes a package substrate 548, 550, and a die 544, 546,the package substrate 548, 550 includes a MEM area 552, 554, and thesupporting substrate 540 supports the ICs 500-502 and includes asupporting substrate micro-electromechanical (MEM) area 542.

As shown, the antenna interface 520, 522 may be within the packagesubstrate MEM area 552, 554 and the antenna structure 524, 526 and theRF bus structure 528 may be within the supporting substrate MEM area542. In this embodiment, the antenna interface 520, 522 is coupled tothe antenna structure 524, 526 by a via and/or a pin on the package ofthe IC 500-502.

FIG. 46 is a diagram of an embodiment of a device that includes theplurality of integrated circuits (ICs) 500-502, the RF bus structure528, and a supporting substrate 540. In this embodiment, each of the ICs500-502 includes a package substrate 548, 550, and a die 544, 546, thepackage substrate 548, 550 includes a MEM area 552, 554, the die 544,546 includes a MEM area 556, 558, and the supporting substrate 540supports the ICs 500-502 and includes a supporting substratemicro-electromechanical (MEM) area 542.

As shown, an impedance matching circuit 560, 562 of the antennainterface 520, 522 is within the die MEM area 556, 558, a transmissionline 564, 566 of the antenna interface 520, 522 is within the packagesubstrate MEM area 552, 554, and the antenna structure 524, 526 and theRF bus structure 528 are within the supporting substrate MEM area 542.Alternatively, the antenna structure 524, 526 may be within the packagesubstrate MEM area 552, 554.

FIG. 47 is a diagram of an embodiment of an intra-device RF buscommunication between two circuit modules of different ICs. In thisembodiment, the antenna structure 524 of a first one of the plurality ofICs 500 has a three-dimensional aperture antenna shape, athree-dimensional lens shape, or a three-dimensional dipole shape (shownas a horn aperture antenna shape). The antenna structure 526 of a secondone of the plurality of ICs 502 has the three-dimensional apertureantenna shape, the three-dimensional lens shape, or thethree-dimensional dipole shape (also shown as a horn aperture antennashape).

The RF bus structure 528 has a three-dimensional waveguide construct(shown as a rectangular tube having a shape approximately equal to theshape of the horn antenna) and is proximally located between the antennastructures 524, 526 of the first and second ones of the plurality of ICs500-502. In this manner, RF bus communications between the ICs can besubstantially contained with the RF bus structure and, with thethree-dimensional antenna design and relatively short travel distances,the transmit power can be very low (e.g., <−50 dBm).

FIG. 48 is a schematic block diagram of another embodiment of a devicethat includes a plurality of integrated circuits (ICs) 570-572 and an RFbus structure 646. Each of the plurality of ICs 570-572 includes aplurality of circuit modules 580-582, 584-586, a plurality of switchingmodules 590-592, 594-596, a plurality of internal RF bus transceivers600-602, 604-606, a plurality of internal RF bus antenna interfaces610-612, 614-616, a plurality of internal RF bus antenna structures620-622, 624-626, an internal RF bus 630, 632, an external busmultiplexer module 634, 636, an external RF bus transceiver 635, 645, anexternal RF bus antenna interface 638, 640, and an external RF busantenna structure 642, 644. The circuit modules 580-586 may be any typeof digital circuit, analog circuit, logic circuit, and/or processingcircuit. For example, one of the circuit modules 580-586 may be, but isnot limited to, a microprocessor, a component of a microprocessor, cachememory, read only memory, random access memory, programmable logic,digital signal processor, logic gate, amplifier, multiplier, adder,multiplexor, etc.

In this embodiment, one or more of the circuit modules 580-584 generatesan outbound bus signal and provides it to a corresponding one of theswitching modules 590-596 (e.g., switching module 590 for circuit module580). The switching module 590-596, which includes a processing moduleand switching elements (e.g., switches, transistors, multiplexers,gates, etc.), determines whether the outbound bus signal is an internalIC communication or an external IC communication.

When the outbound bus communication is an internal IC communication, thecorresponding switching module 590-596 outputs the outbound bus signalvia a first path to a corresponding one of the RF bus transceivers600-606 (e.g., RF bus transceiver 600 for switching module 590). Thecorresponding RF bus transceiver 600-606 converts the outbound bussignal into an outbound RF bus signal, which it provides to acorresponding internal RF bus antenna interface 610-616 (e.g., internalRF bus antenna interface 610 for RF bus transceiver 600). The internalRF bus antenna interface 610, which may include a transformer, animpedance matching circuit, and/or a transmission line, provides theoutbound RF bus signal to a corresponding internal RF bus antennastructure 620-626. The corresponding internal RF bus antenna structure620-626, which may be any one of the antenna structures disclosed inco-pending patent application entitled AN INTEGRATED CIRCUIT ANTENNASTRUCTURE, having a filing date of Dec. 29, 2006, and a Ser. No.11/648,826, transmits the outbound RF bus signal to another antennastructure within the same IC via the internal RF bus 630, 632. Theinternal RF bus 630, 632 includes one or more waveguide RF communicationpaths, one or more dielectric RF communication paths, and/or one or morefree-space RF communication paths.

When the outbound bus communication is an external IC communication, thecorresponding switching module 590-596 outputs the outbound bus signalvia a second path to the external bus multiplexing module 634, 636. Theexternal bus multiplexing module 590-596, which includes control logicand one or more multiplexers, outputs an outbound bus signal from one ofthe plurality of switching module 590-592, 594-596 to the external RFbus transceiver 635, 645. The external RF bus transceiver 635, 645converts the outputted outbound bus signal into an outbound external RFbus signal, which is provided to the external RF bus antenna interface638, 640.

The external RF bus antenna interface 638, 640, which includes atransformer, an impedance matching circuit, and/or a transmission line,provides the outbound external RF bus signal to the external RF busantenna structure 642, 644. The external RF bus antenna structure 642,644, which may be any one of the antenna structures disclosed inco-pending patent application entitled AN INTEGRATED CIRCUIT ANTENNASTRUCTURE, having a filing date of Dec. 29, 2006, and a Ser. No.11/648,826, transmits the outbound external RF bus signal to another IC570, 572 via the external RF bus structure 646. In an embodiment, theexternal RF bus structure includes one or more waveguide RFcommunication paths, one or more dielectric RF communication paths,and/or one or more free-space RF communication paths.

FIG. 49 is a diagram of an embodiment of a device that includes theplurality of integrated circuits (ICs) 570-572, the RF bus structure646, and a supporting substrate 650. In this embodiment, each of the ICs570-572 includes a die 654, 656, and a package substrate 658, 660, thepackage substrate 658, 660 includes a package substrate MEM area 662,664, and the supporting substrate 650 includes a supporting substratemicro-electromechanical (MEM) area 652.

The MEM areas of the package substrate 658, 660 and the supportingsubstrate 650 may be used in a variety of ways to provide the internalIC RF bus communications and the external IC RF bus communications. Forexample, the external RF bus structure 646 may be within the supportingsubstrate MEM area 652 and the internal RF bus structures 630, 632 maybe within the respective package substrate MEM areas 662, 664. Asanother example, the external RF bus antenna interface 638, 640 and theexternal RF bus antenna structure 642, 644 may be within the packagesubstrate MEM area 662, 664. As yet another example, the external RF busantenna interface 638, 640 may be within the package substrate MEM area662, 664 and the external RF bus antenna structure 642, 644 may bewithin the supporting substrate MEM area 652. The later two examples aresimilar to the examples provided in FIGS. 52-53.

In another embodiment, the die 654, 656 may include a die MEM area,which contains therein an impedance matching circuit of one of theplurality of internal RB bus antenna interfaces 610-616. In such anembodiment, a transmission line of one of the plurality of internal RBbus antenna interfaces 610-616, the corresponding internal RF busantenna structure 620-626, and the internal RF bus structure 630-632 maybe within the package substrate MEM area 662, 664.

In an embodiment of an external RF bus communication between two circuitdifferent ICs, the external RF bus antenna structure 642 of one IC 570has a three-dimensional aperture antenna shape, a three-dimensional lensshape, or a three-dimensional dipole shape. The external RF bus antennastructure 644 of a second IC 572 has the three-dimensional apertureantenna shape, the three-dimensional lens shape, or thethree-dimensional dipole shape.

The external RF bus structure 646 has a three-dimensional waveguideconstruct that is proximally located between the external RF bus antennastructures 642, 644 of the ICs 570-572. In this manner, external RF buscommunications between the ICs can be substantially contained with theexternal RF bus structure 6464 and, with the three-dimensional antennadesign and relatively short travel distances, the transmit power can bevery low (e.g., <−50 dBm).

FIG. 50 is a diagram of an embodiment of an IC 500-502, 570-572 thatincludes a plurality of circuit modules 676, 678, an RF bus transceivermodule 680, a die 670, and a package substrate 672. The RF bustransceiver module 680 includes an RF bus transceiver and an antennainterface module. The RF bus transceiver includes a baseband (BB)processing module 682, a transmitter section 684, and a receiver section686. The antenna interface module includes one or more of a transformer688, an impedance matching circuit 690, and a transmission line 692. Thepackage substrate 672 supports the die and includes amicro-electromechanical (MEM) area 674.

In this embodiment, the baseband processing module 682, which may besingle processing device or a plurality of processing devices aspreviously defined, is coupled to convert outbound bus data into anoutbound bus symbol stream. The transmitter section 684 is coupled toconvert the outbound bus symbol stream into an outbound RF bus signal,which is provided to the transformer 688. The transformer 688 includes adifferential winding coupled to the transmitter section 684 and asingle-ended winding coupled to the impedance matching circuit 690.

The impedance matching circuit 690 adjusts gain, phase, and/or impedanceof the single-ended outbound RF bus signal and provides the adjustedsingle-ended outbound RF bus signal to the transmission line 692 forconveyance to an antenna structure. The transmission line 692 is alsocoupled to receive a single-ended inbound RF bus signal from the antennastructure and to provide it to the impedance matching circuit 690.

The impedance matching circuit 690 adjusts gain, phase, and/or impedanceof the single-ended inbound RF bus signal and provides the adjustedsingle-ended outbound RF bus signal to single-ended winding of thetransformer 688. The transformer 688 converts the single-ended inboundRF bus signal into a differential inbound RF bus signal via thedifferential winding or a second differential winding. The transformerprovides the differential inbound RF bus signal to the receiver section686.

The receiver section 686 is coupled to convert an inbound RF bus signalinto an inbound bus symbol stream. The baseband processing module 682converts the inbound bus symbol stream into inbound bus data. In thisembodiment, at least one of the transformer 688, the impedance matchingcircuit 690, and the transmission line 692 is within the MEM area 674.

FIG. 51 is a schematic block diagram of an embodiment of a portion of anRF bus transceiver module 680 that includes the transformer 688, theimpedance matching circuit 690, and the transmission line 692. In thisdiagram, the transformer includes a differential winding and asingle-ended winding; and the impedance matching circuit 690 includes atleast one capacitor and at least one inductor (2 of each are shown, butcould include more or less of each, at least one of the capacitors andinductors may be adjustable or including a selectable network ofcapacitors or inductors). In an embodiment, the transmission line 692,when implemented within the MEM area 674 may have a three-dimensionalshape corresponding to a coaxial cable.

FIG. 52 is a diagram of an embodiment of a three-dimensional inductor ofthe impedance matching circuit 690 and/or a three-dimensionaltransformer 688 implemented within the MEM area 674. The inductor and/ortransformer 688 may have an air core, a ferrite core, or other materialthat provides a medium for electromagnetic waves. The core 694 may be ofany shape to provide the desired magnetic coupling of the winding 696.Note that the transformer 688 would include multiple windings 696.

FIG. 53 is a diagram of an embodiment of a three-dimensional capacitorof the impedance matching circuit 690. The three-dimensional capacitorincludes first and second plates 700 and 702, which may be anyconductive material, and a dielectric 698, which may be air or any othertype of dielectric material that can sustain an electric field. Notethat the shape of the plates 700 and 702 may be square as shown or someother geometric shape.

FIG. 54 is a diagram of an embodiment of a package substrate 672 of anIC. The package substrate 674 includes two MEM areas 674 and 710. Thesecond MEM area 710 supports an RF transmit filter 712, a transmitoscillator (TX OSC) 714, an RF receive filter 716, and/or a receiveoscillator (RX OSC) 718. The RF transmit filter 714 may be a low passfilter, a bandpass filter, or a high pass filter used within thetransmitter section 684.

The transmitter section 684 also includes the transmit oscillator 714,which generates a local oscillation for mixing with the outbound bussymbol stream to produce the outbound RF bus signal. The transmitoscillator 714 may be a phase locked loop, or some other controlledresonating circuit.

The receiver section 686 includes the RF receive filter 716 and areceive oscillator 718. The RF receive filter 716 may be a low passfilter, a bandpass filter, or a high pass filter and the receiveoscillator 718 generates a local oscillation for mixing with the inboundRF bus signal to produce the inbound bus symbol stream. The receiveoscillator 718 may be implement as shown in FIG. 47, may be a phaselocked loop, or some other controlled resonating circuit.

FIG. 55 is a diagram of an embodiment of an IC 500-502, 570-572 thatincludes a plurality of circuit modules 676, 678, an RF bus transceivermodule 680, and a die 720. The RF bus transceiver module 680 includes anRF bus transceiver and an antenna interface module. The RF bustransceiver includes a baseband (BB) processing module 682, atransmitter section 684, and a receiver section 686. The antennainterface module includes one or more of a transformer 688, an impedancematching circuit 690, and a transmission line 692. The die includes amicro-electromechanical (MEM) area 722. In this embodiment, at least oneof the transformer 688, the impedance matching circuit 690, and thetransmission line 692 is within the MEM area 722.

FIG. 56 is a schematic block diagram of an embodiment of an RF buscontroller 1088 that includes an interface 730 and a processing module732. The processing module 732 may be a single processing device or aplurality of processing devices. Such a processing device may be amicroprocessor, micro-controller, digital signal processor,microcomputer, central processing unit, field programmable gate array,programmable logic device, state machine, logic circuitry, analogcircuitry, digital circuitry, and/or any device that manipulates signals(analog and/or digital) based on hard coding of the circuitry and/oroperational instructions. The processing module 732 may have anassociated memory and/or memory element, which may be a single memorydevice, a plurality of memory devices, and/or embedded circuitry of theprocessing module. Such a memory device may be a read-only memory,random access memory, volatile memory, non-volatile memory, staticmemory, dynamic memory, flash memory, cache memory, and/or any devicethat stores digital information. Note that when the processing module732 implements one or more of its functions via a state machine, analogcircuitry, digital circuitry, and/or logic circuitry, the memory and/ormemory element storing the corresponding operational instructions may beembedded within, or external to, the circuitry comprising the statemachine, analog circuitry, digital circuitry, and/or logic circuitry.Further note that, the memory element stores, and the processing module732 executes, hard coded and/or operational instructions correspondingto at least some of the steps and/or functions illustrated in FIGS.65-79.

The interface 730 may be a wireline interface (e.g., an Ethernetconnection, a USB connection, an I2C connection, an I2S connection, orany other type of serial interface) or a wireless interface (e.g., WLAN,WPAN, Intra-device communication, etc.) If the interface 730 is awireless interface, it may include a transceiver module to access acontrol RF communication path having a different frequency than afrequency of the RF bus, a transceiver module to access a control timeslot of a time division multiple access partitioning of the RF bus, atransceiver module to access a control frequency slot of a frequencydivision multiple access partitioning of the RF bus, or a transceivermodule to access the RF bus for communicating the intra-device RF busaccess requests and allocations via a carrier sense multiple access(CSMA) protocol. Regardless of the type of interface, the interface 732is coupled for communicating intra-device RF bus access requests andallocations.

FIG. 57 is a logic diagram of method for controlling access to an RF busthat is performed by the RF bus controller 1088. The method begins atstep 734 where the RF Bus controller 1088 receives an access request toan RF bus via the interface 730. The access request may be received in avariety of ways. For example, the access request may be received inresponse to a polling request, in an allocated time division multipleaccess (TDMA) slot, in response to a token ring passing scheme, inaccordance with a carrier sense multiple access (CSMA) protocol of a RFbus control resource, in accordance with an interrupt protocol, in anallocated frequency division multiple access (FDMA) slot, and/or in anallocated code division multiple access (CDMA) slot.

The method continues at step 736 where the RF bus controller 1088determines RF bus resource availability. This step may also includedetermining an RF bus protocol based on the access request. The RF busprotocol may be a standardized wireless protocol (e.g., GSM, EDGE, GPRS,IEEE 802.11, Bluetooth, etc), a proprietary wireless protocol, and/or amodified standardized wireless protocol (based on one of the standardprotocols but modified, for instance, using an IEEE 802.11 protocol butskipping the interleaving). The determining of the RF bus resourceavailability will be described in greater detail with reference to FIG.66.

The method branches at step 738 based on whether sufficient RF busresources are availability. When sufficient RF bus resources areavailable, the process proceeds to step 740 where the RF bus controllerallocates, via the interface, at least one RF bus resource in responseto the access request. Note that the RF bus resources include, but arenot limited to, a Single Input Single Output (SISO) channel, a MultipleInput Multiple Output (MIMO) channel, multiple SISO channels, multipleMIMO channels, null-reinforce multipath patterning (e.g., use multipathreinforced areas for RF bus communications between two ICs and multipathnulls to block RF bus communications between two ICs), frequency bandselection, a TDMA slot, a CDMA slot, an FDMA slot, an unused free-spaceRF communication path or channel, an unused waveguide RF communicationpath or channel, an unused dielectric RF communication path or channel,and/or any other medium or portioning scheme for transmitting RFsignals.

When sufficient RF bus resources are not available, the method proceedsto step 742 where the RF bus controller 1088 determining what RF busresources are available. The method then proceeds to step 744 where theRF bus controller determines whether the access request can beadequately accommodated by the available RF bus resources. In otherwords, optimal servicing of the original resource request would requirea certain level of RF bus resource allocation based on the amount ofdata to be transmitted, the type of data being transmitted, therequestor of the RF bus access, the target(s) of the data, etc. In thisinstance, the optimal amount of RF bus resources is not available, butthere are some resources available and the RF bus controller isdetermining whether this less than optimal amount of RF bus resourcescan adequately accommodate (e.g., less than optimal, but acceptable) therequest. For example, assume that for a particular RF bus accessrequest, the optimal amount of RF bus resources supports a data transferrate of 100 Mega-bits per second, but that the available RF busresources can only accommodate 66 Mega-bits per second. In this example,the RF bus controller 1088 will determine whether the 66 Mbps rate willaccommodate the request (i.e., won't suffer loss of data integrity, lossof data continuity, etc.).

When the access request can be accommodated by the available RF busresources, the method proceeds to step 746 where the RF bus controller1088 allocates the available RF bus resources to for the access request.If, however, the access request cannot be accommodated by the availableRF bus resources, the method proceeds to step 748 where the RF buscontroller queues the access request.

FIG. 58 is a diagram of another embodiment of a frame 750 of an RF buscommunication that includes a request control slot 752, an allocationcontrol slot 754, and a data slot(s) 756. In this embodiment, the slots752-756 may be TDMA slots, FDMA slots, or CDMA slots on a single channelor multiple channels. Access to the request control slot 752 beallocated to the requesting ICs or circuit modules by the RF buscontroller 1088 in a round robin manner, in a poll-request manner, in aCSMA with collision avoidance manner, etc.

In this embodiment, when an IC or circuit module has data to transmitvia an RF bus (e.g., intra-IC RF bus and/or inter-IC RF bus), therequesting IC or circuit module provides its request within the requestcontrol slot 752. The requesting IC or circuit module waits until itdetects an RF bus grant from the RF bus controller via the allocationcontrol slot 754. The RF bus grant will indicate the RF bus resourcesbeing allocated, the duration of the allocation, etc. and may furtherinclude an indication of the RF bus protocol to be used. Once therequesting IC or circuit module has been granted access, it transmitsits data via the allocated RF bus resources during the appropriate dataslots 756.

FIG. 59 is a logic diagram of method for determining RF bus resourceavailability of step 736 of FIG. 57. This method begins at step 760where the RF bus controller determines transmission requirements of theaccess request, RF bus capabilities of requestor, and/or RF buscapabilities of target. The transmission requirements include one ormore of amount of information to be conveyed, priority level ofrequestor (e.g., application level priority, operating system levelpriority, continuous data priority, discontinuous data priority, etc.),priority level of the information to be conveyed (e.g., applicationdata, interrupt data, operating system data, etc.), real-time ornon-real-time aspect of the information to be conveyed, and/orinformation conveyance integrity requirements.

The conveyance integrity requirements relate to the sensitivity of thedata, the requester, and/or the target is to data transmission errorsand the ability to correct them. Thus, if any of the target or requestoris intolerant to data transmission errors and/or they cannot becorrected, the data needs to be transmitted with the highest level ofintegrity to insure that very few data transmission errors will occur.Conversely, if the requestor and target can tolerate data transmissionerrors and/or can correct them; lower levels of integrity can be used toprovide an adequate RF bus communication. Thus, the RF bus controllermay consider the RF communication paths available (e.g., waveguide,dielectric, free-space), the level of rate encoding, the level ofinterleaving, the level of error correction, and/or the level ofacknowledgement. For example, a request that can tolerate datatransmission errors, the data may be bi-phase encoded with nointerleaving and rate encoding and transmitted over a free-space RFcommunication path, where a request that cannot tolerate datatransmission errors, the data will be encoded using the rate encoding,it will be interleaved, error correction (e.g., forward error correct)enabled, and transmitted over a waveguide RF communication path.

The method then proceeds to step 762 where the RF bus controllerdetermines required RF bus resources based on the at least one of thetransmission requirements, the RF bus capabilities of the requestor, andthe RF bus capabilities of the target. The method then proceeds to step764 where the RF bus controller determines whether the required RF busresources are available for allocation.

FIG. 60 is a logic diagram of another method for controlling access toan RF bus that is performed by the RF bus controller 1088. The methodbegins at step 734 where the RF Bus controller 1088 receives an accessrequest to an RF bus via the interface 730. The access request may bereceived in a variety of ways. For example, the access request may bereceived in response to a polling request, in an allocated time divisionmultiple access (TDMA) slot, in response to a token ring passing scheme,in accordance with a carrier sense multiple access (CSMA) protocol of aRF bus control resource, in accordance with an interrupt protocol, in anallocated frequency division multiple access (FDMA) slot, and/or in anallocated code division multiple access (CDMA) slot.

The method continues at step 736 where the RF bus controller 1088determines RF bus resource availability. This step may also includedetermining an RF bus protocol based on the access request. The RF busprotocol may be a standardized wireless protocol (e.g., GSM, EDGE, GPRS,IEEE 802.11, Bluetooth, etc), a proprietary wireless protocol, and/or amodified standardized wireless protocol (based on one of the standardprotocols but modified, for instance, using an IEEE 802.11 protocol butskipping the interleaving). The determining of the RF bus resourceavailability was described with reference to FIG. 59.

The method branches at step 738 based on whether sufficient RF busresources are availability. When sufficient RF bus resources areavailable, the process proceeds to step 740 where the RF bus controllerallocates, via the interface, at least one RF bus resource in responseto the access request. Note that the RF bus resources include, but arenot limited to, a Single Input Single Output (SISO) channel, a MultipleInput Multiple Output (MIMO) channel, multiple SISO channels, multipleMIMO channels, null-reinforce multipath patterning (e.g., use multipathreinforced areas for RF bus communications between two ICs and multipathnulls to block RF bus communications between two ICs), frequency bandselection, a TDMA slot, a CDMA slot, an FDMA slot, an unused free-spaceRF communication path or channel, an unused waveguide RF communicationpath or channel, an unused dielectric RF communication path or channel,and/or any other medium or portioning scheme for transmitting RFsignals.

When sufficient RF bus resources are not available, the method proceedsto step 766 where the RF bus controller 1088 determines whether priorityof requestor is at or above a first priority level. The priority levelmay be user defined, system defined, an ordering based on data type(e.g., operating system level data, application level data, interruptdata, real-time or continuous data v. non-real-time or discontinuousdata, etc.), system level based (e.g., processing module, memory,peripheral device, etc. in order) and/or any other priority and/orordering scheme. When the request is not above the 1^(st) level, themethod proceeds to step 768 where the RF bus controller queues therequest.

When priority of the requester is at or above the first priority level,the method proceeds to step 770 where the RF bus controller 1088determines whether allocated RF bus resources can be reallocated to makeavailable the sufficient RF bus resources. In this determination, the RFbus controller is determining whether existing RF bus communications canhave their RF bus resources reallocated such that their level of serviceis below optimal, but still acceptable, to make sufficient resourcesavailable for the 1^(st) level or higher priority RF bus request.

When the RF bus resources can be reallocated, the method proceeds tostep 772 where the RF bus controller reallocates at least some of theallocated RF bus resources to make resources available for the 1^(st)level or higher priority RF bus request. The method then proceeds tostep 774 where the RF bus controller 1088 allocates the sufficient RFbus resources to the 1^(st) level or higher priority request.

When the allocated RF bus resources cannot be reallocated and stillprovide an acceptable level of performance, the RF bus controller 1088determines whether the priority of the requester is of a second prioritylevel (i.e., of the highest level that if its request is not timelysatisfied, the entire system or device may lock up). If the priority isnot at the 2^(nd) level, the method proceeds to step 768 where the RFbus controller 1088 queues the request.

If, however, the priority level of the requestor is of the secondpriority level, the method proceeds to step 778 where the RF buscontroller reclaims RF bus resources from the allocated RF bus resourcesto provide the sufficient RF bus resources. In other words, the RF buscontroller cancels a current RF bus communication to reclaim them forthe 2^(nd) priority level request. In one embodiment, the current RF buscommunication having the most tolerance to a data transmissioninterruption is selected for reclaiming the RF bus resources. The methodthen proceeds to step 780 where the RF bus controller 1088 allocates thereclaimed RF bus resources to the 2^(nd) priority level requester.

FIG. 61 is a schematic block diagram of another embodiment of amillimeter wave interface 1080 that includes a requestor IC or circuitmodule 790, a target IC or circuit module 792, the RF bus controller1088, a system level RF bus 814, and an application level RF bus 816.The requestor 790 and the target 792 each include an RF bus transceiver974. The RF bus transceiver 794 includes a programmable encode/decodemodule 796, a programmable interleave/deinterleave module 798, aprogrammable map/demap module 800, an inverse fast Fourier transform(IFFT)/FFT module 804, an RF front-end 804, and a plurality ofmultiplexers 806-810. The system level RF bus 814 and the applicationlevel RF bus 816 each include one or more waveguide RF communicationpaths, one or more dielectric RF communication paths, and/or one or morefree-space RF communication paths.

In this embodiment, the RF bus controller 1088 controls access to thesystem level RF bus 814 for operating system level data conveyances andcontrols access to the application level RF bus 816 for applicationlevel data conveyances. Such data conveyances may include controlinformation, operational instructions, and/or data (e.g., raw data,intermediate data, processed data, and/or stored data that includes textinformation, numerical information, video files, audio files, graphics,etc.).

In addition to controlling access to the RF buses 814 and 816, the RFbus controller 1088 may indicate to the RF bus transceivers 794 the RFbus protocol to be used for converting outbound data into outbound RFbus signals. For example, the RF bus protocol may be a standardizedwireless protocol (e.g., IEEE 802.11, Bluetooth, GSM, EDGE, GPRS, CDMA,etc.), may be a proprietary wireless protocol, or a modified standardwireless protocol.

For example, if the RF bus controller 1088 indicates using a standardIEEE 802.11 wireless protocol (e.g., IEEE 802.11a, b, g, n, etc.), theRF bus transceiver 794 enables the programmable modules 796, 798, and800 and the multiplexers 806-810 to perform in accordance with the IEEE802.11 standard. For instance, multiplexer 806 provides outbound data tothe programmable encoding/decoding module 706 that performs a half rate(or other rate) convolution encoding on the outbound data to produceencoded data. The programmable encoding/decoding module 706 may furtherpuncture the encoded data to produce punctured data.

Continuing with the example, the encoded or punctured data is outputtedto multiplexer 808, which provides the data to the programmableinterleave/deinterleave module 708. The programmableinterleave/deinterleave module 708 interleaves bits of different encodeddata words to produce interleaved data. Multiplexer 810 provides theinterleaved data to the programmable map/demap module 800 which maps theinterleaved data to produce mapped data. The mapped data is convertedfrom the frequency domain to the time domain by the IFFT portion of theIFFT/FFT module 802 to produce an outbound symbol stream. Multiplexer810 provides the outbound symbol stream to the RF front end 804, whichincludes an RF transmitter section and an RF receiver section. The RFtransmitter section converts the outbound symbol stream into an outboundRF bus signal.

The target 792 receives the outbound RF bus signal via the system levelRF bus 814 or the application level RF bus 816 via its RF bustransceiver 794. The receiver section of the RF front end 804 convertsthe received RF bus signal into an inbound symbol stream. The FFTportion of the IFFT/FFT module 802 converts the inbound symbol streamfrom the time domain to the frequency domain to produce inbound mappeddata. The programmable map/demap module 800 demaps the inbound mappeddata to produce inbound interleaved data. Multiplexer 810 provides theinbound interleaved data to the programmable interleave/deinterleavemodule 798, which deinterleaves the inbound interleaved data to produceencoded or punctured data. The programmable encoding/decoding module 796depunctures and/or decodes the encoded or punctured data to recapturethe data.

As an example of a modified standard wireless protocol, multiplexer 806provides outbound data to the programmable encoding/decoding module 706that performs a half rate (or other rate) convolution encoding on theoutbound data in accordance with a standard wireless protocol (e.g.,IEEE 802.11) to produce encoded data. The programmable encoding/decodingmodule 706 may further puncture the encoded data to produce punctureddata.

Continuing with the example, the encoded or punctured data is outputtedto multiplexer 808, which provides the data to the programmablemap/demap module 800 which maps the encoded or punctured data to producemapped data. The mapped data is converted from the frequency domain tothe time domain by the IFFT portion of the IFFT/FFT module 802 toproduce an outbound symbol stream. Multiplexer 810 provides the outboundsymbol stream to the RF transmitter section, which converts the outboundsymbol stream into an outbound RF bus signal. As illustrated by thisexample, a modified standard wireless protocol is based on a standardwireless protocol with one or more of its functional steps omitted ormodified.

As another example of a modified standard wireless protocol, multiplexer806 provides outbound data to the programmable map/demap module 800which maps the outbound data to produce mapped data. The mapped data isconverted from the frequency domain to the time domain by the IFFTportion of the IFFT/FFT module 802 to produce an outbound symbol stream,which is subsequently converted into the outbound RF bus signal.

As an example of a proprietary RF bus protocol, multiplexer 806 providesoutbound data to the programmable encoding/decoding module 706 thatperforms a bi-phase, return to zero (RTZ), non-return to zero (NRZ),and/or another binary encoding scheme to produce binary encoded data.The binary encoded data may be provided directly to the RF front end 804via multiplexers 808 and 812, to the programmableinterleave/deinterleave module 798 via multiplexer 808, or to theprogrammable map/demap module 800 via multiplexers 808 and 810.

The programmable map/demap module 800 may be programmed to map/demapdata in a variety of ways. For example, the programmable map/demapmodule 800 may map the data into Cartesian coordinates having anin-phase component (e.g., A₁(t)cos ω(t)) and a quadrature component(e.g., A_(Q)(t)sin ω(t)). As another example, the programmable map/demapmodule 800 may map the data into polar coordinates (e.g.,A(t)cos(ω(t)+φ(t))). As yet another example, the programmable map/demapmodule 800 may map the data into hybrid coordinates having a normalizedin-phase component (e.g., cos(ω(t)+φ(t)) and a normalized quadraturecomponent (e.g., sin(ω(t)+φ(t))).

FIG. 62 is a logic diagram of another method for controlling access toan RF bus. The method begins at step 818 where the RF bus controllerdetermines access requirements to an RF bus. The access requirements mayinclude system configuration information, system level RF bus resources,application level RF bus resources, RF bus capabilities of requestor, RFbus capabilities of target, amount of information to be conveyed,priority level of requestor, priority level of the information to beconveyed, real-time or non-real-time aspect of the information to beconveyed, and/or information conveyance integrity requirements.

The system configuration information includes number of ICs in thedevice, number of circuit modules in the ICs, nulling and reinforcingpatterns, number and type of intra-device RF data bus, number and typeof intra-device RF instruction bus, number and type of intra-device RFcontrol bus, number and type of intra-IC RF data bus, number and type ofintra-IC RF instruction bus, number and type of intra-IC RF control bus,types of ICs in the device, and/or bus interface capabilities of the ICsand/or its circuit modules. Note that the information conveyanceintegrity requirements include level of rate encoding (e.g., ½ rate, ¾rate, etc.), level of interleaving, level of error correction, and/orlevel of acknowledgement (e.g., whether an ACK back is required or not,if required content of the ACK). Further note that the system level RFbus resources and the application level RF bus resources includes aSingle Input Single Output (SISO) channel, a Multiple Input MultipleOutput (MIMO) channel, multiple SISO channels, multiple MIMO channels,null-reinforce multipath patterning, frequency band selection, waveguideRF path, dielectric RF path, free space RF path, time division multipleaccess (TDMA) time slot, frequency division multiple access (FDMA)frequency slot, code division multiple access (CDMA) code slot,proprietary resource, and carrier sense multiple access (CSMA).

The method then proceeds to step 820 where the RF bus controllerdetermines RF bus resource available. This step may further includedetermining an RF bus protocol based on the access request, wherein theRF bus protocol is one of: a standardized wireless protocol, aproprietary wireless protocol, and a modified standardized wirelessprotocol.

The method then proceeds to step 822 where the RF bus controllerallocates, via the interface, RF bus resources in accordance with theaccess requirements and the RF bus resource availability. This may bedone by determining whether sufficient RF bus resources are available tofulfill the access requirements; when the sufficient RF bus resourcesare available to fulfill the access request, allocating the sufficientRF bus resources to a requester; when the sufficient RF bus resourcesare not available to fulfill the access request, determining availableRF bus resources; determining whether the access requirements can beaccommodated by the available RF bus resources; when the access requestcan be accommodated by the available RF bus resources, allocating theavailable RF bus resources to the requestor; and when the access requestcannot be accommodated by the available RF bus resources, queuing theaccess requirements.

The method may further include, when the sufficient RF bus resources arenot available to fulfill the access requirements, the RF bus controllerdetermining whether priority of the requestor is at or above a firstpriority level; when priority of the requestor is at or above the firstpriority level, determining whether allocated RF bus resources can bereallocated to make available the sufficient RF bus resources; when theallocated RF bus resources can be reallocated, reallocating at leastsome of the allocated RF bus resources; when the RF bus resources cannotbe reallocated, determining whether the priority of the requestor is ofa second priority level; when the priority level of the requester is ofthe second priority level, reclaiming RF bus resources from theallocated RF bus resources to provide the sufficient RF bus resources;and when the priority level of the requestor is below the secondpriority level, queuing the access requirements.

FIG. 63 is a logic diagram of another method for controlling access toan RF bus. The method begins at step 824 where the RF bus controllerdetermines access requirements to an RF bus for a circuit of anintegrated circuit (IC) of a plurality of integrated circuits. This maybe done as previously discussed. The method then proceeds to step 826where the RF bus controller determines whether the access requirementspertain to an inter-IC communication or an intra-IC communication.

The method then proceeds to step 828 where the RF bus controller 1088determines RF bus resource available in accordance with inter-ICcommunication or the intra-IC communication. This may be done aspreviously described. The method then proceeds to step 830 where the RFbus controller allocates, via the interface, RF bus resources inaccordance with the access requirements and the RF bus resourceavailability.

FIG. 64 is a schematic block diagram of an embodiment of an RF bustransceiver 840 that may be used as or in combination with RF bustransceiver 1108, 110, 130, 150, 152, 180-186, 210, 212, 232, 234, 235,236, 238, 240, 258, 260, 280, 344, 354, 516, 518, 600-604, 635, 645,680, and/or 794. The RF bus transceiver 840 includes a transmitter 842and a receiver 844. The transmitter 842 performs the methods of FIGS. 57and 59 and the receiver 844 performs the method of FIG. 58.

FIG. 65 is a logic diagram of method for RF bus transmitting that beginsat step 846 where the transmitter 842 determine whether outboundinformation is to be transmitted via the RF bus. Such a determinationmay be made by setting a flag by the IC or circuit module that includesthe RF bus transceiver, by providing the outbound information to the RFbus transceiver, and/or any other mechanism for notifying that it hasinformation to transmit.

When the outbound information is to be transmitted via the RF bus, themethod proceeds to step 848 where the transmitter 842 determines whetherthe RF bus is available. When the RF bus is not available, thetransmitter 842 waits until the RF bus becomes available. Thetransmitter 842 may determine by the availability of the RF bus byutilizing a carrier sense multiple access with collision avoidance(CSMA/CD) access protocol, utilizing a request to send frame and clearto send frame exchange access protocol, utilizing a poll-response accessprotocol, interpreting a control time slot of a time division multipleaccess (TDMA) frame, interpreting a control frequency slot of afrequency division multiple access (FDMA) frame, interpreting a controlcode slot of a code division multiple access (CDMA) frame, and/orutilizing a request-grant access protocol.

When the RF bus is available, the method proceeds to step 850 where thetransmitter 842 secures access to the RF bus. The transmitter 842 maysecure access to the RF bus by accessing the RF bus in accordance with acarrier sense multiple access with collision avoidance (CSMA/CD) accessprotocol, accessing the RF bus in response to a favorable request tosend frame and clear to send frame exchange, accessing the RF bus inaccordance with a poll-response access protocol, accessing the RF busvia an allocated time slot of a time division multiple access (TDMA)frame, accessing the RF bus via an allocated frequency slot of afrequency division multiple access (FDMA) frame, accessing the RF busvia an allocated code slot of a code division multiple access (CDMA)frame, and/or accessing the RF bus in accordance with a request-grantaccess protocol. Note that the transmitter 842 may determine whether theRF bus is available and secures access to the RF bus by communicatingwith the RF bus controller 1088 via a wireline link, via a wirelesslink, and/or via the RF bus.

The method proceeds to step 852 where the transmitter 842 converts theoutbound information into outbound RF bus signal. The method thenproceeds to step 844 where the transmitter 842 transmits the outbound RFbus signal via the RF bus when access to the RF bus is secured. As such,the transmitter 842 prepares data for transmission via one of the RFbuses in a device and transmits the RF bus signal when it is thetransmitter's turn and/or when the RF bus is not in use.

FIG. 66 is a logic diagram of method for RF bus receiving that begins atstep 856 where the receiver 844 determines whether inbound informationis to be received via the RF bus. The receiver 844 may determine thatthere is inbound information to be received by utilizing a carrier sensemultiple access with collision avoidance (CSMA/CD) access protocol,utilizing a request to send frame and clear to send frame exchangeaccess protocol, utilizing a poll-response access protocol, interpretinga control time slot of a time division multiple access (TDMA) frame,interpreting a control frequency slot of a frequency division multipleaccess (FDMA) frame, interpreting a control code slot of a code divisionmultiple access (CDMA) frame, and/or utilizing a request-grant accessprotocol.

When there is inbound information to be received via the RF bus, themethod proceeds to step 858 where the receiver 844 determines accessparameters to the RF bus for receiving the inbound information. Thereceiver 844 may determine the access parameters by receiving theinbound RF bus signal in accordance with a carrier sense multiple accesswith collision avoidance (CSMA/CD) access protocol, receiving theinbound RF bus signal in accordance with a request to send frame andclear to send frame exchange, receiving the inbound RF bus signal inaccordance with a poll-response access protocol, receiving the inboundRF bus signal via an allocated time slot of a time division multipleaccess (TDMA) frame, receiving the inbound RF bus signal via anallocated frequency slot of a frequency division multiple access (FDMA)frame, receiving the inbound RF bus signal via an allocated code slot ofa code division multiple access (CDMA) frame, and/or receiving theinbound RF bus signal in accordance with a request-grant accessprotocol. Note that the receiver 844 may determine the access parametersby communicating with the RF bus controller 1088 via a wireline link, awireless link, and/or the RF bus.

The method then proceeds to step 860 where the receiver 844 receives aninbound RF bus signal during the access to the RF bus in accordance withthe access parameters. The method then proceeds to step 862 where thereceiver 844 converts the inbound RF bus signal into the inboundinformation.

FIG. 67 is a logic diagram of method for determining whether informationis to be transmitted via an RF bus by the transmitter 842. The methodbegins at step 870 where the transmitter 842 identifies a target of theoutbound information. In one embodiment, the outbound information willbe in packet or frame format having a header portion that includes theaddress of the source, the address of the destination, the size of thepacket or frame, etc.

The method then proceeds to step 872 where the transmitter 842determines whether the target is accessible via the RF bus. The targetmay not be accessible via the RF bus for several reasons. For example,the nature of the data being transmitted may require that it betransmitted via a wireline link, the target may be in a multipath nullwith respect to the source, the target is currently using the RF bus foranother RF bus communication, etc. When the target is not accessible viathe RF bus, the method proceeds to step 876 where the transmitter 842sends the outbound information via a wireline link.

When the target is accessible via the RF bus, the method proceeds tostep 874 where the transmitter determines the type of the outboundinformation to be transmitted. When the type of the outbound informationis of a first type (e.g., tolerant of transmission errors), the methodproceeds to step 878 where the transmitter 842 indicates that theoutbound information is to be transmitted via the RF bus. When the typeof the outbound information is of a second type (e.g., not tolerant oftransmission errors), the method proceeds to step 876 where thetransmitter 842 indicates that the outbound information is to betransmitted via a wireline link. Note that step 874 could be omitted.

FIG. 68 is a schematic block diagram of an embodiment of a transmitter842 of an RF bus transceiver 840. The transmitter 842 includes abaseband processing module 880, an up-conversion module 882, and an RFtransmitter 884. The baseband (BB) processing module 880 may be a singleprocessing device or a plurality of processing devices. Such aprocessing device may be a microprocessor, micro-controller, digitalsignal processor, microcomputer, central processing unit, fieldprogrammable gate array, programmable logic device, state machine, logiccircuitry, analog circuitry, digital circuitry, and/or any device thatmanipulates signals (analog and/or digital) based on hard coding of thecircuitry and/or operational instructions. The BB processing module 880may have an associated memory and/or memory element, which may be asingle memory device, a plurality of memory devices, and/or embeddedcircuitry of the processing module. Such a memory device may be aread-only memory, random access memory, volatile memory, non-volatilememory, static memory, dynamic memory, flash memory, cache memory,and/or any device that stores digital information. Note that when the BBprocessing module 880 implements one or more of its functions via astate machine, analog circuitry, digital circuitry, and/or logiccircuitry, the memory and/or memory element storing the correspondingoperational instructions may be embedded within, or external to, thecircuitry comprising the state machine, analog circuitry, digitalcircuitry, and/or logic circuitry.

In operation, the baseband processing module 880 is coupled to convertthe outbound information 886 into a baseband or near baseband symbolstream 888 (e.g., a symbol stream having a carrier frequency of 0 Hz toa few MHz). The baseband processing module 880 functions to convertingthe outbound information into a baseband or near baseband symbol streamby utilizing a standard single input single output data modulationprotocol, utilizing a proprietary single input single output datamodulation protocol, utilizing a modified standard single input singleoutput data modulation protocol, utilizing a standard multiple inputmultiple output data modulation protocol, utilizing a proprietarymultiple input multiple output data modulation protocol, utilizing amodified standard multiple input multiple output data modulationprotocol, and/or utilizing a baseband beamforming data modulationprotocol.

The up-conversion module 882, embodiments of which will be described ingreater detail with reference to FIGS. 69-71, is coupled to up-convertthe baseband or near baseband symbol stream 888 into an up-convertedsignal 890. The RF transmitter 884 is coupled to transmit theup-converted signal 890 as the RF bus signal 892 in accordance with anRF transmission setting. The RF transmission setting includestransmitting multiple phase adjusted representations of the up-convertedsignal as the RF bus signal in accordance with an in-air beamforming RFtransmission setting, transmitting the RF bus signal via a waveguide inaccordance with a waveguide RF transmission setting, and/or transmittingthe RF bus signal via free space in accordance with a free space RFtransmission setting.

FIG. 69 is a schematic block diagram of an embodiment of anup-conversion module 882 of a transmitter 842. The up-conversion module882 includes a first mixer 906, a second mixer 908, a ninety degreephase shift module, and a combining module 910. In this embodiment, theup-conversion module 882 converts a Cartesian-based baseband or nearbaseband symbol stream 888 into the up-converted signal 890.

In this embodiment, the first mixer 906 mixes an in-phase component 902of the baseband or near baseband symbol stream 888 with an in-phasecomponent of the transmit local oscillation 900 to produce a first mixedsignal. The second mixer 908 mixes a quadrature component 904 of thebaseband or near baseband symbol stream 888 with a quadrature componentof the transmit local oscillation to produce a second mixed signal. Thecombining module 910 combines the first and second mixed signals toproduce the up-converted signal 890.

For example, if the I component 902 is expressed as A₁cos(ω_(dn)+Φ_(n)), the Q component 904 is expressed as A_(Q)sin(ω_(dn)+Φ_(n)), the I component of the local oscillation 900 isexpressed as cos(ω_(RF)) and the Q component of the local oscillation900 is represented as sin(ω_(RF)), then the first mixed signal is ½ A₁cos(ω_(RF)−ω_(dn)−Φ_(n))+½ A₁ cos(ω_(RF)+ω_(dn)+Φ_(n)) and the secondmixed signal is ½ A_(Q) cos(ω_(RF)−ω_(dn)−Φ_(n))−½ A_(Q)cos(ω_(RF)+ω_(dn)+Φ_(n)). The combining module 910 then combines the twosignals to produce the up-converted signal 890, which may be expressedas A cos(ω_(RF)+ω_(dn)+Φ_(n)). Note that the combining module 910 may bea subtraction module, may be a filtering module, and/or any othercircuit to produce the up-converted signal from the first and secondmixed signals.

FIG. 70 is a schematic block diagram of an embodiment of anup-conversion module 882 of a transmitter 842. In this embodiment, theup-conversion module 882 includes an oscillation module 911 and convertsphase modulation information 912 of the baseband or near baseband symbolstream 888 into the up-converted signal 890.

In operation, the oscillation module 911, which may be a phase lockedloop, a fractional N synthesizer, and/or other oscillation generatingcircuit, utilizes the transmit local oscillation 900 as a referenceoscillation to produce an oscillation at the frequency of theup-converted signal 890. The phase of the oscillation is adjusted inaccordance with the phase modulation information 912 of the baseband ornear baseband symbol stream 888 to produce the up-converted signal 890.

FIG. 71 is a schematic block diagram of an embodiment of anup-conversion module 882 of a transmitter 842. In this embodiment, theup-conversion module 882 includes the oscillation module 911 and amultiplier 914 to convert phase modulation information 912 and amplitudemodulation information 916 of the baseband or near baseband symbolstream 888 to produce the up-converted signal 890.

In operation, the oscillation module 911, which may be a phase lockedloop, a fractional N synthesizer, and/or other oscillation generatingcircuit, utilizes the transmit local oscillation 900 as a referenceoscillation to produce an oscillation at the frequency of theup-converted signal 890. The phase of the oscillation is adjusted inaccordance with the phase modulation information 912 of the baseband ornear baseband symbol stream 888 to produce a phase modulated RF signal.The multiplier 914 multiplies the phase modulated RF signal withamplitude modulation information 916 of the baseband or near basebandsymbol stream 888 to produce the up-converted signal 890.

FIG. 72 is a schematic block diagram of an embodiment of the receiver844 of the RF bus transceiver 840. The receiver 844 includes an RFreceiver 920, a down-conversion module 922, and a baseband processingmodule 924. The baseband (BB) processing module 924 may be a singleprocessing device or a plurality of processing devices. Such aprocessing device may be a microprocessor, micro-controller, digitalsignal processor, microcomputer, central processing unit, fieldprogrammable gate array, programmable logic device, state machine, logiccircuitry, analog circuitry, digital circuitry, and/or any device thatmanipulates signals (analog and/or digital) based on hard coding of thecircuitry and/or operational instructions. The BB processing module 924may have an associated memory and/or memory element, which may be asingle memory device, a plurality of memory devices, and/or embeddedcircuitry of the processing module. Such a memory device may be aread-only memory, random access memory, volatile memory, non-volatilememory, static memory, dynamic memory, flash memory, cache memory,and/or any device that stores digital information. Note that when the BBprocessing module 924 implements one or more of its functions via astate machine, analog circuitry, digital circuitry, and/or logiccircuitry, the memory and/or memory element storing the correspondingoperational instructions may be embedded within, or external to, thecircuitry comprising the state machine, analog circuitry, digitalcircuitry, and/or logic circuitry.

In operation, the RF receiver 920 is coupled to convert the RF bussignal 892 into an up-converted signal 890 in accordance with the RFtransmission setting. The down-conversion module 922 is coupled todown-convert the up-converted signal to produce a baseband or nearbaseband symbol stream 888. The baseband processing module 924 iscoupled to convert the baseband or near baseband symbol stream 888 intothe information 886. The baseband processing module 924 may use convertthe baseband or near baseband symbol stream into the information byutilizing a standard single input single output data demodulationprotocol, utilizing a proprietary single input single output datademodulation protocol, utilizing a modified standard single input singleoutput data demodulation protocol, utilizing a standard multiple inputmultiple output data demodulation protocol, utilizing a proprietarymultiple input multiple output data demodulation protocol, utilizing amodified standard multiple input multiple output data demodulationprotocol, and utilizing a baseband beamforming data demodulationprotocol.

As may be used herein, the terms “substantially” and “approximately”provides an industry-accepted tolerance for its corresponding termand/or relativity between items. Such an industry-accepted toleranceranges from less than one percent to fifty percent and corresponds to,but is not limited to, component values, integrated circuit processvariations, temperature variations, rise and fall times, and/or thermalnoise. Such relativity between items ranges from a difference of a fewpercent to magnitude differences. As may also be used herein, theterm(s) “coupled to” and/or “coupling” and/or includes direct couplingbetween items and/or indirect coupling between items via an interveningitem (e.g., an item includes, but is not limited to, a component, anelement, a circuit, and/or a module) where, for indirect coupling, theintervening item does not modify the information of a signal but mayadjust its current level, voltage level, and/or power level. As mayfurther be used herein, inferred coupling (i.e., where one element iscoupled to another element by inference) includes direct and indirectcoupling between two items in the same manner as “coupled to”. As mayeven further be used herein, the term “operable to” indicates that anitem includes one or more of power connections, input(s), output(s),etc., to perform one or more its corresponding functions and may furtherinclude inferred coupling to one or more other items. As may stillfurther be used herein, the term “associated with”, includes directand/or indirect coupling of separate items and/or one item beingembedded within another item. As may be used herein, the term “comparesfavorably”, indicates that a comparison between two or more items,signals, etc., provides a desired relationship. For example, when thedesired relationship is that signal 1 has a greater magnitude thansignal 2, a favorable comparison may be achieved when the magnitude ofsignal 1 is greater than that of signal 2 or when the magnitude ofsignal 2 is less than that of signal 1.

While the transistors in the above described figure(s) is/are shown asfield effect transistors (FETs), as one of ordinary skill in the artwill appreciate, the transistors may be implemented using any type oftransistor structure including, but not limited to, bipolar, metal oxidesemiconductor field effect transistors (MOSFET), N-well transistors,P-well transistors, enhancement mode, depletion mode, and zero voltagethreshold (VT) transistors.

The present invention has also been described above with the aid ofmethod steps illustrating the performance of specified functions andrelationships thereof. The boundaries and sequence of these functionalbuilding blocks and method steps have been arbitrarily defined hereinfor convenience of description. Alternate boundaries and sequences canbe defined so long as the specified functions and relationships areappropriately performed. Any such alternate boundaries or sequences arethus within the scope and spirit of the claimed invention.

The present invention has been described above with the aid offunctional building blocks illustrating the performance of certainsignificant functions. The boundaries of these functional buildingblocks have been arbitrarily defined for convenience of description.Alternate boundaries could be defined as long as the certain significantfunctions are appropriately performed. Similarly, flow diagram blocksmay also have been arbitrarily defined herein to illustrate certainsignificant functionality. To the extent used, the flow diagram blockboundaries and sequence could have been defined otherwise and stillperform the certain significant functionality. Such alternatedefinitions of both functional building blocks and flow diagram blocksand sequences are thus within the scope and spirit of the claimedinvention. One of average skill in the art will also recognize that thefunctional building blocks, and other illustrative blocks, modules andcomponents herein, can be implemented as illustrated or by discretecomponents, application specific integrated circuits, processorsexecuting appropriate software and the like or any combination thereof.

1. A flash memory device comprising: a flash memory; a host interfacemodule that couples the flash memory to a host device, the hostinterface module including: a millimeter wave transceiver coupled towirelessly communicate read commands, write commands, read data andwrite data between the host interface module and the host device over amillimeter wave communication path in accordance with a host interfaceprotocol; a protocol conversion module coupled to convert the readcommands, the write commands and the write data from the host interfaceprotocol and to convert the read data to the host interface protocol;and a host module coupled to decode the read commands and the writecommands from the host device, to process the read commands to retrievethe read data from the flash memory and to process the write commands towrite the write data to the flash memory; and a millimeter wavecommunication path to wirelessly couple the host interface module to theflash memory within the flash memory device, in which the millimeterwave communication path operates as a wireless connectivity to transferthe read data and the write data between the host interface module andthe flash memory.
 2. The flash memory device of claim 1 wherein the hostmodule includes a processing device to arbitrate the execution of readand write commands and the wireless flow of data between the hostinterface module and the flash memory.
 3. The flash memory device ofclaim 1 wherein the host interface protocol includes at least one of:direct memory access (DMA), Advanced Technology Attachment (ATA), SerialATA (SATA), Fibre channel ATA (FATA), Small Computer System Interface(SCSI), Integrated Drive Electronics (IDE), Enhanced IDE (EIDE),MultiMedia Card (MMC), Universal Serial Bus (USB), Serial Attached SCSI(SAS) and Compact Flash (CF).
 4. The flash memory device of claim 1wherein the host interface protocol operates in accordance with aprotocol stack having a physical layer, a link layer, a command layerand a transport layer interface between the flash memory and the hostdevice.
 5. The flash memory device of claim 4 wherein the physical layerand the link layer operate in accordance with a millimeter waveprotocol.
 6. A method for use in a flash memory device, the methodcomprising: wirelessly communicating read commands, write commands, readdata and write data between a host interface module and a host deviceover a millimeter wave communication path in accordance with a hostinterface protocol; and converting the read commands, the write commandsand the write data from the host interface protocol; converting the readdata to the host interface protocol; and performing wireless datatransfers between the host interface module and a flash memory disposedwithin the device, wherein a millimeter wave communication path is usedto wirelessly couple the host interface module to the flash memory, inwhich the millimeter wave communication path operates as a wirelessconnectivity to transfer the read data and the write data between thehost interface module and the flash memory.
 7. The method of claim 6wherein the host interface protocol includes at least one of: AdvancedTechnology Attachment (ATA), Serial ATA (SATA), Fibre channel ATA(FATA), Small Computer System Interface (SCSI), Integrated DriveElectronics (IDE), Enhanced IDE (EIDE), MultiMedia Card (MMC), UniversalSerial Bus (USB), Serial Attached SCSI (SAS) and Compact Flash (CF). 8.The method of claim 6 wherein the host interface protocol operates inaccordance with a protocol stack having a physical layer, a link layer,a command layer and a transport layer interface between the flash memoryand the host device.
 9. The method of claim 8 wherein the physical layerand the link layer operate in accordance with a millimeter waveprotocol.